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Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the disassembler tables. Add PINSRWrr64i to complement the AVX version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192565 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2710,6 +2710,7 @@ multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
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!strconcat(asm, "\t{$src, $dst|$dst, $src}"),
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[(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
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Sched<[WriteVecLogic]>;
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let isAsmParserOnly = 1, hasSideEffects = 0 in
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def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
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!strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
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IIC_SSE_MOVMSK, d>, REX_W, Sched<[WriteVecLogic]>;
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@ -4284,14 +4285,21 @@ def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
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// Insert
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let Predicates = [HasAVX] in {
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defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
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let isAsmParserOnly = 1, hasSideEffects = 0 in
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def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
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"vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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[]>, TB, OpSize, VEX_4V, Sched<[WriteShuffle]>;
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}
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let Constraints = "$src1 = $dst" in
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defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[UseSSE2]>;
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let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in {
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defm PINSRW : sse2_pinsrw, TB, OpSize;
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let isAsmParserOnly = 1, hasSideEffects = 0 in
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def PINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
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"pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[]>, TB, OpSize, Sched<[WriteShuffle]>;
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} // Predicates = [UseSSE2], Constraints = "$src1 = $dst"
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} // ExeDomain = SSEPackedInt
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@ -235,3 +235,11 @@ sha256msg2 (%rax), %xmm2
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// CHECK: pmovmskb %xmm5, %rcx
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// CHECK: encoding: [0x66,0x0f,0xd7,0xcd]
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pmovmskb %xmm5,%rcx
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// CHECK: pinsrw $3, %ecx, %xmm5
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// CHECK: encoding: [0x66,0x0f,0xc4,0xe9,0x03]
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pinsrw $3, %ecx, %xmm5
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// CHECK: pinsrw $3, %rcx, %xmm5
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// CHECK: encoding: [0x66,0x0f,0xc4,0xe9,0x03]
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pinsrw $3, %rcx, %xmm5
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