mirror of
https://github.com/RPCS3/llvm.git
synced 2025-04-14 12:01:21 +00:00
RegScavenger interface change to make it more flexible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34690 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
171eed5334
commit
bb6fb3357d
@ -27,16 +27,34 @@ class TargetRegisterClass;
|
|||||||
class RegScavenger {
|
class RegScavenger {
|
||||||
MachineBasicBlock *MBB;
|
MachineBasicBlock *MBB;
|
||||||
MachineBasicBlock::iterator MBBI;
|
MachineBasicBlock::iterator MBBI;
|
||||||
bool MBBIInited;
|
|
||||||
unsigned NumPhysRegs;
|
unsigned NumPhysRegs;
|
||||||
|
|
||||||
|
/// Initialized - All states are initialized and ready to go!
|
||||||
|
bool Initialized;
|
||||||
|
|
||||||
/// RegStates - The current state of all the physical registers immediately
|
/// RegStates - The current state of all the physical registers immediately
|
||||||
/// before MBBI. One bit per physical register. If bit is set that means it's
|
/// before MBBI. One bit per physical register. If bit is set that means it's
|
||||||
/// available, unset means the register is currently being used.
|
/// available, unset means the register is currently being used.
|
||||||
BitVector RegStates;
|
BitVector RegStates;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
RegScavenger(MachineBasicBlock *mbb);
|
RegScavenger()
|
||||||
|
: MBB(NULL), Initialized(false) {};
|
||||||
|
|
||||||
|
RegScavenger(MachineBasicBlock *mbb)
|
||||||
|
: MBB(mbb), Initialized(false) {};
|
||||||
|
|
||||||
|
/// Init - Initialize the states.
|
||||||
|
///
|
||||||
|
void init();
|
||||||
|
|
||||||
|
/// Reset - Discard previous states and re-initialize the states given for
|
||||||
|
/// the specific basic block.
|
||||||
|
void reset(MachineBasicBlock *mbb) {
|
||||||
|
MBB = mbb;
|
||||||
|
clear();
|
||||||
|
init();
|
||||||
|
}
|
||||||
|
|
||||||
/// forward / backward - Move the internal MBB iterator and update register
|
/// forward / backward - Move the internal MBB iterator and update register
|
||||||
/// states.
|
/// states.
|
||||||
@ -45,8 +63,12 @@ public:
|
|||||||
|
|
||||||
/// forward / backward - Move the internal MBB iterator and update register
|
/// forward / backward - Move the internal MBB iterator and update register
|
||||||
/// states until it has reached but not processed the specific iterator.
|
/// states until it has reached but not processed the specific iterator.
|
||||||
void forward(MachineBasicBlock::iterator I);
|
void forward(MachineBasicBlock::iterator I) {
|
||||||
void backward(MachineBasicBlock::iterator I);
|
while (MBBI != I) forward();
|
||||||
|
}
|
||||||
|
void backward(MachineBasicBlock::iterator I) {
|
||||||
|
while (MBBI != I) backward();
|
||||||
|
}
|
||||||
|
|
||||||
/// isReserved - Returns true if a register is reserved. It is never "unused".
|
/// isReserved - Returns true if a register is reserved. It is never "unused".
|
||||||
bool isReserved(unsigned Reg) const { return ReservedRegs[Reg]; }
|
bool isReserved(unsigned Reg) const { return ReservedRegs[Reg]; }
|
||||||
@ -69,10 +91,16 @@ public:
|
|||||||
bool ExCalleeSaved = false) const;
|
bool ExCalleeSaved = false) const;
|
||||||
|
|
||||||
private:
|
private:
|
||||||
|
/// clear - Clear states.
|
||||||
|
///
|
||||||
|
void clear();
|
||||||
|
|
||||||
/// CalleeSavedrRegs - A bitvector of callee saved registers for the target.
|
/// CalleeSavedrRegs - A bitvector of callee saved registers for the target.
|
||||||
|
///
|
||||||
BitVector CalleeSavedRegs;
|
BitVector CalleeSavedRegs;
|
||||||
|
|
||||||
/// ReservedRegs - A bitvector of reserved registers.
|
/// ReservedRegs - A bitvector of reserved registers.
|
||||||
|
///
|
||||||
BitVector ReservedRegs;
|
BitVector ReservedRegs;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -25,12 +25,12 @@
|
|||||||
#include "llvm/ADT/STLExtras.h"
|
#include "llvm/ADT/STLExtras.h"
|
||||||
using namespace llvm;
|
using namespace llvm;
|
||||||
|
|
||||||
RegScavenger::RegScavenger(MachineBasicBlock *mbb)
|
void RegScavenger::init() {
|
||||||
: MBB(mbb), MBBIInited(false) {
|
|
||||||
const MachineFunction &MF = *MBB->getParent();
|
const MachineFunction &MF = *MBB->getParent();
|
||||||
const TargetMachine &TM = MF.getTarget();
|
const TargetMachine &TM = MF.getTarget();
|
||||||
const MRegisterInfo *RegInfo = TM.getRegisterInfo();
|
const MRegisterInfo *RegInfo = TM.getRegisterInfo();
|
||||||
|
|
||||||
|
MBBI = MBB->begin();
|
||||||
NumPhysRegs = RegInfo->getNumRegs();
|
NumPhysRegs = RegInfo->getNumRegs();
|
||||||
RegStates.resize(NumPhysRegs, true);
|
RegStates.resize(NumPhysRegs, true);
|
||||||
|
|
||||||
@ -50,15 +50,16 @@ RegScavenger::RegScavenger(MachineBasicBlock *mbb)
|
|||||||
for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
|
for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
|
||||||
E = MBB->livein_end(); I != E; ++I)
|
E = MBB->livein_end(); I != E; ++I)
|
||||||
setUsed(*I);
|
setUsed(*I);
|
||||||
|
|
||||||
|
Initialized = true;
|
||||||
}
|
}
|
||||||
|
|
||||||
void RegScavenger::forward() {
|
void RegScavenger::forward() {
|
||||||
assert(MBBI != MBB->end() && "Already at the end of the basic block!");
|
assert(MBBI != MBB->end() && "Already at the end of the basic block!");
|
||||||
// Move ptr forward.
|
// Move ptr forward.
|
||||||
if (!MBBIInited) {
|
if (!Initialized)
|
||||||
MBBI = MBB->begin();
|
init();
|
||||||
MBBIInited = true;
|
else
|
||||||
} else
|
|
||||||
MBBI = next(MBBI);
|
MBBI = next(MBBI);
|
||||||
|
|
||||||
MachineInstr *MI = MBBI;
|
MachineInstr *MI = MBBI;
|
||||||
@ -133,16 +134,6 @@ void RegScavenger::backward() {
|
|||||||
setUsed(ChangedRegs);
|
setUsed(ChangedRegs);
|
||||||
}
|
}
|
||||||
|
|
||||||
void RegScavenger::forward(MachineBasicBlock::iterator I) {
|
|
||||||
while (MBBI != I)
|
|
||||||
forward();
|
|
||||||
}
|
|
||||||
|
|
||||||
void RegScavenger::backward(MachineBasicBlock::iterator I) {
|
|
||||||
while (MBBI != I)
|
|
||||||
backward();
|
|
||||||
}
|
|
||||||
|
|
||||||
/// CreateRegClassMask - Set the bits that represent the registers in the
|
/// CreateRegClassMask - Set the bits that represent the registers in the
|
||||||
/// TargetRegisterClass.
|
/// TargetRegisterClass.
|
||||||
static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {
|
static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {
|
||||||
@ -167,3 +158,14 @@ unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
|
|||||||
int Reg = RegStatesCopy.find_first();
|
int Reg = RegStatesCopy.find_first();
|
||||||
return (Reg == -1) ? 0 : Reg;
|
return (Reg == -1) ? 0 : Reg;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void RegScavenger::clear() {
|
||||||
|
if (MBB) {
|
||||||
|
MBBI = MBB->end();
|
||||||
|
MBB = NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
NumPhysRegs = 0;
|
||||||
|
Initialized = false;
|
||||||
|
RegStates.clear();
|
||||||
|
}
|
||||||
|
Loading…
x
Reference in New Issue
Block a user