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remove the V8 simple isel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25534 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -22,7 +22,6 @@ namespace llvm {
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class FunctionPass;
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class TargetMachine;
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FunctionPass *createSparcV8SimpleInstructionSelector(TargetMachine &TM);
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FunctionPass *createSparcV8ISelDag(TargetMachine &TM);
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FunctionPass *createSparcV8CodePrinterPass(std::ostream &OS,
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@ -27,10 +27,6 @@ using namespace llvm;
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namespace {
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// Register the target.
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RegisterTarget<SparcV8TargetMachine> X("sparcv8"," SPARC V8 (experimental)");
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cl::opt<bool> EnableV8DAGDAG("enable-v8-dag-isel", cl::Hidden,
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cl::desc("Enable DAG-to-DAG isel for V8"),
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cl::init(0));
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}
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/// SparcV8TargetMachine ctor - Create an ILP32 architecture model
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@ -83,18 +79,10 @@ bool SparcV8TargetMachine::addPassesToEmitFile(PassManager &PM,
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if (PrintMachineCode)
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PM.add(new PrintFunctionPass());
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if (!EnableV8DAGDAG) {
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// Replace malloc and free instructions with library calls.
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PM.add(createLowerAllocationsPass());
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PM.add(createLowerSelectPass());
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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PM.add(createSparcV8SimpleInstructionSelector(*this));
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} else {
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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PM.add(createSparcV8ISelDag(*this));
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}
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// Print machine instructions as they were initially generated.
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if (PrintMachineCode)
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File diff suppressed because it is too large
Load Diff
@ -22,7 +22,6 @@ namespace llvm {
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class FunctionPass;
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class TargetMachine;
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FunctionPass *createSparcV8SimpleInstructionSelector(TargetMachine &TM);
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FunctionPass *createSparcV8ISelDag(TargetMachine &TM);
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FunctionPass *createSparcV8CodePrinterPass(std::ostream &OS,
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File diff suppressed because it is too large
Load Diff
@ -27,10 +27,6 @@ using namespace llvm;
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namespace {
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// Register the target.
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RegisterTarget<SparcV8TargetMachine> X("sparcv8"," SPARC V8 (experimental)");
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cl::opt<bool> EnableV8DAGDAG("enable-v8-dag-isel", cl::Hidden,
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cl::desc("Enable DAG-to-DAG isel for V8"),
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cl::init(0));
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}
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/// SparcV8TargetMachine ctor - Create an ILP32 architecture model
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@ -83,18 +79,10 @@ bool SparcV8TargetMachine::addPassesToEmitFile(PassManager &PM,
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if (PrintMachineCode)
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PM.add(new PrintFunctionPass());
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if (!EnableV8DAGDAG) {
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// Replace malloc and free instructions with library calls.
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PM.add(createLowerAllocationsPass());
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PM.add(createLowerSelectPass());
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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PM.add(createSparcV8SimpleInstructionSelector(*this));
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} else {
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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PM.add(createSparcV8ISelDag(*this));
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}
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// Print machine instructions as they were initially generated.
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if (PrintMachineCode)
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