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Improve comment to make explicit why not to touch this could before JIT goes MC

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111021 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2010-08-13 17:44:10 +00:00
parent c92bb50a0c
commit bbadd39bbb
1 changed files with 6 additions and 1 deletions
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7
lib/Target/X86/X86InstrSSE.td
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@ -2174,7 +2174,9 @@ def : Pat<(X86SFence), (SFENCE)>;
// Alias instructions that map zero vector to pxor / xorp* for sse.
// We set canFoldAsLoad because this can be converted to a constant-pool
// load of an all-zeros value if folding it would be beneficial.
// FIXME: Change encoding to pseudo!
// FIXME: Change encoding to pseudo! This is blocked right now by the x86
// JIT implementatioan, it does not expand the instructions below like
// X86MCInstLower does.
let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
isCodeGenOnly = 1 in {
def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
@ -2188,6 +2190,9 @@ def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
// The same as done above but for AVX. The 128-bit versions are the
// same, but re-encoded. The 256-bit does not support PI version.
// FIXME: Change encoding to pseudo! This is blocked right now by the x86
// JIT implementatioan, it does not expand the instructions below like
// X86MCInstLower does.
let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
isCodeGenOnly = 1, Predicates = [HasAVX] in {
def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",