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Remove the bare getSubtargetImpl call from the PPC port. As part

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of this add a test that shows we can generate code with
for functions that differ by subtarget feature.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232882 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2015-03-21 03:36:02 +00:00
parent f2b4a7f862
commit bc473edd7b
3 changed files with 44 additions and 5 deletions
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3
lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -163,8 +163,7 @@ PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
: LLVMTargetMachine(T, getDataLayoutString(Triple(TT)), TT, CPU,
computeFSAdditions(FS, OL, TT), Options, RM, CM, OL),
TLOF(createTLOF(Triple(getTargetTriple()))),
TargetABI(computeTargetABI(Triple(TT), Options)),
Subtarget(TT, CPU, TargetFS, *this) {
TargetABI(computeTargetABI(Triple(TT), Options)) {
initAsmInfo();
}

3
lib/Target/PowerPC/PPCTargetMachine.h
View File

@ -29,8 +29,6 @@ public:
private:
std::unique_ptr<TargetLoweringObjectFile> TLOF;
PPCABI TargetABI;
PPCSubtarget Subtarget;
mutable StringMap<std::unique_ptr<PPCSubtarget>> SubtargetMap;
public:
@ -40,7 +38,6 @@ public:
~PPCTargetMachine() override;
const PPCSubtarget *getSubtargetImpl() const override { return &Subtarget; }
const PPCSubtarget *getSubtargetImpl(const Function &F) const override;
// Pass Pipeline Configuration

43
test/CodeGen/PowerPC/ppc-crbits-onoff.ll Normal file
View File

@ -0,0 +1,43 @@
; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind readnone
define signext i32 @crbitsoff(i32 signext %v1, i32 signext %v2) #0 {
entry:
%tobool = icmp ne i32 %v1, 0
%lnot = icmp eq i32 %v2, 0
%and3 = and i1 %tobool, %lnot
%and = zext i1 %and3 to i32
ret i32 %and
; CHECK-LABEL: @crbitsoff
; CHECK-DAG: cmplwi {{[0-9]+}}, 3, 0
; CHECK-DAG: li [[REG2:[0-9]+]], 1
; CHECK-DAG: cntlzw [[REG3:[0-9]+]],
; CHECK: isel 3, 0, [[REG2]]
; CHECK: and 3, 3, [[REG3]]
; CHECK: blr
}
define signext i32 @crbitson(i32 signext %v1, i32 signext %v2) #1 {
entry:
%tobool = icmp ne i32 %v1, 0
%lnot = icmp eq i32 %v2, 0
%and3 = and i1 %tobool, %lnot
%and = zext i1 %and3 to i32
ret i32 %and
; CHECK-LABEL: @crbitson
; CHECK-DAG: cmpwi {{[0-9]+}}, 3, 0
; CHECK-DAG: cmpwi {{[0-9]+}}, 4, 0
; CHECK-DAG: li [[REG2:[0-9]+]], 1
; CHECK-DAG: crorc [[REG3:[0-9]+]],
; CHECK: isel 3, 0, [[REG2]], [[REG3]]
; CHECK: blr
}
attributes #0 = { nounwind readnone "target-features"="-crbits" }
attributes #1 = { nounwind readnone }