[AArch64][Falkor] Fix sched details for FMOV of WZR/XZR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303680 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Geoff Berry 2017-05-23 19:54:28 +00:00
parent 4868a15090
commit bcb35301da
2 changed files with 8 additions and 6 deletions

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@ -430,12 +430,12 @@ def : InstRW<[FalkorWr_FMUL64_1VXVY_6cyc, ReadDefault, ReadDefault, FalkorReadFM
// FP Miscellaneous Instructions
// -----------------------------------------------------------------------------
def : InstRW<[FalkorWr_FMOV], (instregex "^FMOV(H|S|D)i$")>;
def : InstRW<[FalkorWr_1GTOV_1cyc], (instregex "^FMOV(HW|HX|SW|DX|DXHigh)r$")>;
def : InstRW<[FalkorWr_FMOV], (instregex "^FMOV(WH|WS|XH|XD|XDHigh)r$")>;
def : InstRW<[FalkorWr_1GTOV_1cyc], (instregex "^FMOV(H|S|D)i$")>;
def : InstRW<[FalkorWr_1VTOG_1cyc], (instregex "^FCVTZ(S|U)(S|U)(W|X)(D|S)ri?$")>;
def : InstRW<[FalkorWr_1VTOG_1cyc], (instregex "^FMOV(WH|WS|XH|XD|XDHigh)r$")>;
def : InstRW<[FalkorWr_1VTOG_1cyc], (instregex "^FMOV(HW|HX|SW|DX|DXHigh)r$")>;
def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^FMOV(Hr|Sr|Dr|v.*_ns)$")>;
// FIXME: We are currently generating movi v0.2d, #0 for these, which is worse than fmov 0.0
// FIXME: We are currently generating movi v0.2d, #0 for these, which is worse than fmov wzr/xzr
def : InstRW<[FalkorWr_2VXVY_1cyc], (instrs FMOVD0, FMOVS0)>;
def : InstRW<[FalkorWr_1GTOV_4cyc], (instregex "^(S|U)CVTF(S|U)(W|X)(D|S)ri$")>;

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@ -376,11 +376,13 @@ def FalkorReadFMA64 : SchedReadAdvance<2, [FalkorWr_FMUL64_1VXVY_6cyc, FalkorWr
// SchedPredicates and WriteVariants for Immediate Zero and LSLFast
// -----------------------------------------------------------------------------
def FalkorImmZPred : SchedPredicate<[{MI->getOperand(1).getImm() == 0}]>;
def FalkorFMOVZrReg : SchedPredicate<[{MI->getOperand(1).getReg() == AArch64::WZR ||
MI->getOperand(1).getReg() == AArch64::XZR}]>;
def FalkorLSLFastPred : SchedPredicate<[{TII->isFalkorLSLFast(*MI)}]>;
def FalkorWr_FMOV : SchedWriteVariant<[
SchedVar<FalkorImmZPred, [FalkorWr_1none_0cyc]>,
SchedVar<NoSchedPred, [FalkorWr_1GTOV_1cyc]>]>;
SchedVar<FalkorFMOVZrReg, [FalkorWr_1none_0cyc]>,
SchedVar<NoSchedPred, [FalkorWr_1GTOV_1cyc]>]>;
def FalkorWr_MOVZ : SchedWriteVariant<[
SchedVar<FalkorImmZPred, [FalkorWr_1none_0cyc]>,