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Remove target specific node MipsISD::CMov, which is not used because all conditional moves are directly matched using tablegen patterns. If there's a need in the future, we can introduce it again
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121164 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -41,7 +41,6 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case MipsISD::Lo : return "MipsISD::Lo";
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case MipsISD::GPRel : return "MipsISD::GPRel";
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case MipsISD::Ret : return "MipsISD::Ret";
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case MipsISD::CMov : return "MipsISD::CMov";
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case MipsISD::SelectCC : return "MipsISD::SelectCC";
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case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
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case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
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@ -40,9 +40,6 @@ namespace llvm {
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// Handle gp_rel (small data/bss sections) relocation.
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GPRel,
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// Conditional Move
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CMov,
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// Select CC Pseudo Instruction
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SelectCC,
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@ -52,9 +52,6 @@ def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
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// Select Condition Code
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def MipsSelectCC : SDNode<"MipsISD::SelectCC", SDT_MipsSelectCC>;
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// Conditional Move
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def MipsCMov : SDNode<"MipsISD::CMov", SDT_MipsCMov>;
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//===----------------------------------------------------------------------===//
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// Mips Instruction Predicate Definitions.
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//===----------------------------------------------------------------------===//
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@ -306,8 +303,7 @@ class ByteSwap<bits<6> func, string instr_asm>:
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class CondMov<bits<6> func, string instr_asm, PatLeaf MovCode>:
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FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$F, CPURegs:$T,
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CPURegs:$cond), !strconcat(instr_asm, "\t$dst, $T, $cond"),
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[(set CPURegs:$dst, (MipsCMov CPURegs:$F, CPURegs:$T,
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CPURegs:$cond, MovCode))], NoItinerary>;
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[], NoItinerary>;
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//===----------------------------------------------------------------------===//
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// Pseudo instructions
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