Remove target specific node MipsISD::CMov, which is not used because all conditional moves are directly matched using tablegen patterns. If there's a need in the future, we can introduce it again

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121164 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2010-12-07 19:04:14 +00:00
parent ab8d53a56a
commit bd3af09cef
3 changed files with 1 additions and 9 deletions

View File

@ -41,7 +41,6 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
case MipsISD::Lo : return "MipsISD::Lo";
case MipsISD::GPRel : return "MipsISD::GPRel";
case MipsISD::Ret : return "MipsISD::Ret";
case MipsISD::CMov : return "MipsISD::CMov";
case MipsISD::SelectCC : return "MipsISD::SelectCC";
case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
case MipsISD::FPBrcond : return "MipsISD::FPBrcond";

View File

@ -40,9 +40,6 @@ namespace llvm {
// Handle gp_rel (small data/bss sections) relocation.
GPRel,
// Conditional Move
CMov,
// Select CC Pseudo Instruction
SelectCC,

View File

@ -52,9 +52,6 @@ def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
// Select Condition Code
def MipsSelectCC : SDNode<"MipsISD::SelectCC", SDT_MipsSelectCC>;
// Conditional Move
def MipsCMov : SDNode<"MipsISD::CMov", SDT_MipsCMov>;
//===----------------------------------------------------------------------===//
// Mips Instruction Predicate Definitions.
//===----------------------------------------------------------------------===//
@ -306,8 +303,7 @@ class ByteSwap<bits<6> func, string instr_asm>:
class CondMov<bits<6> func, string instr_asm, PatLeaf MovCode>:
FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$F, CPURegs:$T,
CPURegs:$cond), !strconcat(instr_asm, "\t$dst, $T, $cond"),
[(set CPURegs:$dst, (MipsCMov CPURegs:$F, CPURegs:$T,
CPURegs:$cond, MovCode))], NoItinerary>;
[], NoItinerary>;
//===----------------------------------------------------------------------===//
// Pseudo instructions