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[mips][sched] Split IIFmulDouble into II_MUL_D, II_MADD_D, II_MSUB_D, II_NMADD_D, and II_NMSUB_S

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No functional change since the InstrItinData's have been duplicated.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199737 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2014-01-21 13:07:31 +00:00
parent c55cf21ac0
commit be0843e767
3 changed files with 26 additions and 18 deletions
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14
lib/Target/Mips/MicroMipsInstrFPU.td
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@ -12,7 +12,7 @@ def FADD_MM : MMRel, ADDS_FT<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>,
ADDS_FM_MM<1, 0x30>;
def FDIV_MM : MMRel, ADDS_FT<"div.d", AFGR64Opnd, IIFdivDouble, 0, fdiv>,
ADDS_FM_MM<1, 0xf0>;
def FMUL_MM : MMRel, ADDS_FT<"mul.d", AFGR64Opnd, IIFmulDouble, 1, fmul>,
def FMUL_MM : MMRel, ADDS_FT<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>,
ADDS_FM_MM<1, 0xb0>;
def FSUB_MM : MMRel, ADDS_FT<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>,
ADDS_FM_MM<1, 0x70>;
@ -137,12 +137,12 @@ def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
MADDS_FM_MM<0x22>;
def MADD_D32_MM : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, IIFmulDouble, fadd>,
def MADD_D32_MM : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
MADDS_FM_MM<0x9>;
def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, IIFmulDouble, fsub>,
def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
MADDS_FM_MM<0x29>;
def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, IIFmulDouble,
fadd>, MADDS_FM_MM<0xa>;
def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, IIFmulDouble,
fsub>, MADDS_FM_MM<0x2a>;
def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
MADDS_FM_MM<0xa>;
def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
MADDS_FM_MM<0x2a>;
}

18
lib/Target/Mips/MipsInstrFPU.td
View File

@ -427,7 +427,7 @@ def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, IIFdivSingle, 0, fdiv>,
defm FDIV : ADDS_M<"div.d", IIFdivDouble, 0, fdiv>, ADDS_FM<0x03, 17>;
def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
ADDS_FM<0x02, 16>;
defm FMUL : ADDS_M<"mul.d", IIFmulDouble, 1, fmul>, ADDS_FM<0x02, 17>;
defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>;
def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
ADDS_FM<0x01, 16>;
defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>;
@ -447,31 +447,31 @@ let Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in {
}
let Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in {
def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, IIFmulDouble, fadd>,
def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
MADDS_FM<4, 1>;
def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, IIFmulDouble, fsub>,
def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
MADDS_FM<5, 1>;
}
let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in {
def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, IIFmulDouble, fadd>,
def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
MADDS_FM<6, 1>;
def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, IIFmulDouble, fsub>,
def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
MADDS_FM<7, 1>;
}
let Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in {
def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, IIFmulDouble, fadd>,
def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
MADDS_FM<4, 1>;
def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, IIFmulDouble, fsub>,
def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
MADDS_FM<5, 1>;
}
let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc],
isCodeGenOnly=1 in {
def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, IIFmulDouble, fadd>,
def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
MADDS_FM<6, 1>;
def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, IIFmulDouble, fsub>,
def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>,
MADDS_FM<7, 1>;
}

12
lib/Target/Mips/MipsSchedule.td
View File

@ -20,7 +20,6 @@ def IIAlu : InstrItinClass;
def IILoad : InstrItinClass;
def IIStore : InstrItinClass;
def IIBranch : InstrItinClass;
def IIFmulDouble : InstrItinClass;
def IIFdivSingle : InstrItinClass;
def IIFdivDouble : InstrItinClass;
def IIFsqrtSingle : InstrItinClass;
@ -72,6 +71,7 @@ def II_FLOOR : InstrItinClass;
def II_LUI : InstrItinClass;
def II_MADD : InstrItinClass;
def II_MADDU : InstrItinClass;
def II_MADD_D : InstrItinClass;
def II_MADD_S : InstrItinClass;
def II_MFHI_MFLO : InstrItinClass; // mfhi and mflo
def II_MOVF : InstrItinClass;
@ -90,14 +90,18 @@ def II_MOV_D : InstrItinClass;
def II_MOV_S : InstrItinClass;
def II_MSUB : InstrItinClass;
def II_MSUBU : InstrItinClass;
def II_MSUB_D : InstrItinClass;
def II_MSUB_S : InstrItinClass;
def II_MTHI_MTLO : InstrItinClass; // mthi and mtlo
def II_MUL : InstrItinClass;
def II_MULT : InstrItinClass;
def II_MULTU : InstrItinClass;
def II_MUL_D : InstrItinClass;
def II_MUL_S : InstrItinClass;
def II_NEG : InstrItinClass;
def II_NMADD_D : InstrItinClass;
def II_NMADD_S : InstrItinClass;
def II_NMSUB_D : InstrItinClass;
def II_NMSUB_S : InstrItinClass;
def II_NOR : InstrItinClass;
def II_OR : InstrItinClass;
@ -216,7 +220,11 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
InstrItinData<II_MSUB_S , [InstrStage<7, [ALU]>]>,
InstrItinData<II_NMADD_S , [InstrStage<7, [ALU]>]>,
InstrItinData<II_NMSUB_S , [InstrStage<7, [ALU]>]>,
InstrItinData<IIFmulDouble , [InstrStage<8, [ALU]>]>,
InstrItinData<II_MUL_D , [InstrStage<8, [ALU]>]>,
InstrItinData<II_MADD_D , [InstrStage<8, [ALU]>]>,
InstrItinData<II_MSUB_D , [InstrStage<8, [ALU]>]>,
InstrItinData<II_NMADD_D , [InstrStage<8, [ALU]>]>,
InstrItinData<II_NMSUB_D , [InstrStage<8, [ALU]>]>,
InstrItinData<IIFdivSingle , [InstrStage<23, [ALU]>]>,
InstrItinData<IIFdivDouble , [InstrStage<36, [ALU]>]>,
InstrItinData<IIFsqrtSingle , [InstrStage<54, [ALU]>]>,