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Add a mysteriously missing libcall, FPTOSINT_F80_I32.
Be nice to 16 bit machines by supporting FP_TO_XINT expansion for these. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53407 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -97,6 +97,7 @@ namespace RTLIB {
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FPTOSINT_F64_I32,
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FPTOSINT_F64_I64,
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FPTOSINT_F64_I128,
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FPTOSINT_F80_I32,
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FPTOSINT_F80_I64,
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FPTOSINT_F80_I128,
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FPTOSINT_PPCF128_I32,
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@ -3770,6 +3770,10 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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LC = RTLIB::FPTOSINT_F32_I32;
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else if (OVT == MVT::f64)
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LC = RTLIB::FPTOSINT_F64_I32;
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else if (OVT == MVT::f80)
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LC = RTLIB::FPTOSINT_F80_I32;
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else if (OVT == MVT::ppcf128)
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LC = RTLIB::FPTOSINT_PPCF128_I32;
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else
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assert(0 && "Unexpected i32-to-fp conversion!");
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} else if (VT == MVT::i64) {
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@ -536,6 +536,9 @@ SDOperand DAGTypeLegalizer::SoftenFloatOp_FP_TO_SINT(SDNode *N) {
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case MVT::f64:
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LC = RTLIB::FPTOSINT_F64_I32;
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break;
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case MVT::f80:
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LC = RTLIB::FPTOSINT_F80_I32;
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break;
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case MVT::ppcf128:
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LC = RTLIB::FPTOSINT_PPCF128_I32;
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break;
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@ -444,6 +444,7 @@ SDOperand DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
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return Tmp;
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}
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//===----------------------------------------------------------------------===//
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// Integer Operand Promotion
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//===----------------------------------------------------------------------===//
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@ -995,7 +996,17 @@ void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDOperand &Lo,
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MVT VT = N->getValueType(0);
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SDOperand Op = N->getOperand(0);
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RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
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if (VT == MVT::i64) {
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if (VT == MVT::i32) {
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if (Op.getValueType() == MVT::f32)
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LC = RTLIB::FPTOSINT_F32_I32;
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else if (Op.getValueType() == MVT::f64)
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LC = RTLIB::FPTOSINT_F64_I32;
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else if (Op.getValueType() == MVT::f80)
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LC = RTLIB::FPTOSINT_F80_I32;
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else if (Op.getValueType() == MVT::ppcf128)
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LC = RTLIB::FPTOSINT_PPCF128_I32;
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} else if (VT == MVT::i64) {
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if (Op.getValueType() == MVT::f32)
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LC = RTLIB::FPTOSINT_F32_I64;
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else if (Op.getValueType() == MVT::f64)
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@ -1013,9 +1024,8 @@ void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDOperand &Lo,
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LC = RTLIB::FPTOSINT_F80_I128;
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else if (Op.getValueType() == MVT::ppcf128)
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LC = RTLIB::FPTOSINT_PPCF128_I128;
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} else {
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assert(0 && "Unexpected fp-to-sint conversion!");
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}
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assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
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SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi);
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}
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@ -1024,7 +1034,16 @@ void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDOperand &Lo,
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MVT VT = N->getValueType(0);
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SDOperand Op = N->getOperand(0);
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RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
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if (VT == MVT::i64) {
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if (VT == MVT::i32) {
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if (Op.getValueType() == MVT::f32)
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LC = RTLIB::FPTOUINT_F32_I32;
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else if (Op.getValueType() == MVT::f64)
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LC = RTLIB::FPTOUINT_F64_I32;
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else if (Op.getValueType() == MVT::f80)
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LC = RTLIB::FPTOUINT_F80_I32;
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else if (Op.getValueType() == MVT::ppcf128)
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LC = RTLIB::FPTOUINT_PPCF128_I32;
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} else if (VT == MVT::i64) {
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if (Op.getValueType() == MVT::f32)
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LC = RTLIB::FPTOUINT_F32_I64;
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else if (Op.getValueType() == MVT::f64)
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@ -1042,9 +1061,8 @@ void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDOperand &Lo,
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LC = RTLIB::FPTOUINT_F80_I128;
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else if (Op.getValueType() == MVT::ppcf128)
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LC = RTLIB::FPTOUINT_PPCF128_I128;
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} else {
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assert(0 && "Unexpected fp-to-uint conversion!");
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}
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assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
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SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi);
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}
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@ -95,6 +95,7 @@ static void InitLibcallNames(const char **Names) {
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Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
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Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
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Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
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Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
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Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
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Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
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Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
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