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ARM: fix literal load with positive offset encoding

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When using a positive offset, literal loads where encoded
as if it was negative, because:
- The sign bit was not assigned to an operand
- The addrmode_imm12 operand was not encoding the sign bit correctly

This patch also makes the assembler look at the .w/.n specifier for
loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184182 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Amaury de la Vieuville 2013-06-18 08:13:05 +00:00
parent f8b60d6f30
commit beb920fce6
4 changed files with 27 additions and 6 deletions
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6
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -1024,16 +1024,16 @@ multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
opc, ".w\t$Rt, $addr",
[(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
bits<4> Rt;
bits<13> addr;
let isReMaterializable = 1;
let Inst{31-27} = 0b11111;
let Inst{26-25} = 0b00;
let Inst{24} = signed;
let Inst{23} = ?; // add = (U == '1')
let Inst{23} = addr{12}; // add = (U == '1')
let Inst{22-21} = opcod;
let Inst{20} = 1; // load
let Inst{19-16} = 0b1111; // Rn
bits<4> Rt;
bits<12> addr;
let Inst{15-12} = Rt{3-0};
let Inst{11-0} = addr{11-0};

4
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -5862,7 +5862,9 @@ processInstruction(MCInst &Inst,
case ARM::t2LDRpcrel:
// Select the narrow version if the immediate will fit.
if (Inst.getOperand(1).getImm() > 0 &&
Inst.getOperand(1).getImm() <= 0xff)
Inst.getOperand(1).getImm() <= 0xff &&
!(static_cast<ARMOperand*>(Operands[2])->isToken() &&
static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
Inst.setOpcode(ARM::tLDRpci);
else
Inst.setOpcode(ARM::t2LDRpci);

2
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
View File

@ -743,10 +743,10 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
if (!MO.isReg()) {
Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
Imm12 = 0;
isAdd = false ; // 'U' bit is set as part of the fixup.
if (MO.isExpr()) {
const MCExpr *Expr = MO.getExpr();
isAdd = false ; // 'U' bit is set as part of the fixup.
MCFixupKind Kind;
if (isThumb2())

21
test/MC/ARM/basic-thumb2-instructions.s
View File

@ -3515,12 +3515,31 @@ _func:
@------------------------------------------------------------------------------
@ Alternate syntax for LDR*(literal) encodings
@------------------------------------------------------------------------------
ldrb r11, [pc, #22]
ldrh r11, [pc, #22]
ldrsb r11, [pc, #22]
ldrsh r11, [pc, #22]
ldr.w r11, [pc, #22]
ldrb.w r11, [pc, #22]
ldrh.w r11, [pc, #22]
ldrsb.w r11, [pc, #22]
ldrsh.w r11, [pc, #22]
@ CHECK: ldrb.w r11, [pc, #22] @ encoding: [0x9f,0xf8,0x16,0xb0]
@ CHECK: ldrh.w r11, [pc, #22] @ encoding: [0xbf,0xf8,0x16,0xb0]
@ CHECK: ldrsb.w r11, [pc, #22] @ encoding: [0x9f,0xf9,0x16,0xb0]
@ CHECK: ldrsh.w r11, [pc, #22] @ encoding: [0xbf,0xf9,0x16,0xb0]
@ CHECK: ldr.w r11, [pc, #22] @ encoding: [0xdf,0xf8,0x16,0xb0]
@ CHECK: ldrb.w r11, [pc, #22] @ encoding: [0x9f,0xf8,0x16,0xb0]
@ CHECK: ldrh.w r11, [pc, #22] @ encoding: [0xbf,0xf8,0x16,0xb0]
@ CHECK: ldrsb.w r11, [pc, #22] @ encoding: [0x9f,0xf9,0x16,0xb0]
@ CHECK: ldrsh.w r11, [pc, #22] @ encoding: [0xbf,0xf9,0x16,0xb0]
ldr r11, [pc, #-22]
ldrb r11, [pc, #-22]
ldrh r11, [pc, #-22]
ldrsb r11, [pc, #-22]
ldrsh r11, [pc, #-22]
ldr.w r11, [pc, #-22]
ldrb.w r11, [pc, #-22]
ldrh.w r11, [pc, #-22]