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add fneg/fabs support for doubles

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24847 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-12-19 00:50:12 +00:00
parent da5a7fd8d4
commit beecfd2b2d
4 changed files with 74 additions and 34 deletions
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42
lib/Target/Sparc/FPMover.cpp
View File

@ -84,27 +84,39 @@ bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
bool Changed = false; bool Changed = false;
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) { for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
MachineInstr *MI = I++; MachineInstr *MI = I++;
if (MI->getOpcode() == V8::FpMOVD) { if (MI->getOpcode() == V8::FpMOVD || MI->getOpcode() == V8::FpABSD ||
MI->getOpcode() == V8::FpNEGD) {
Changed = true;
unsigned DestDReg = MI->getOperand(0).getReg(); unsigned DestDReg = MI->getOperand(0).getReg();
unsigned SrcDReg = MI->getOperand(1).getReg(); unsigned SrcDReg = MI->getOperand(1).getReg();
if (DestDReg != SrcDReg || MI->getOpcode() != V8::FpMOVD) { if (DestDReg == SrcDReg && MI->getOpcode() == V8::FpMOVD) {
unsigned EvenSrcReg = 0, OddSrcReg = 0, EvenDestReg = 0, OddDestReg = 0; MBB.erase(MI); // Eliminate the noop copy.
getDoubleRegPair(DestDReg, EvenDestReg, OddDestReg); ++NoopFpDs;
getDoubleRegPair(SrcDReg, EvenSrcReg, OddSrcReg); continue;
}
unsigned EvenSrcReg = 0, OddSrcReg = 0, EvenDestReg = 0, OddDestReg = 0;
getDoubleRegPair(DestDReg, EvenDestReg, OddDestReg);
getDoubleRegPair(SrcDReg, EvenSrcReg, OddSrcReg);
I->setOpcode(V8::FMOVS); if (MI->getOpcode() == V8::FpMOVD)
I->SetMachineOperandReg(0, EvenDestReg); MI->setOpcode(V8::FMOVS);
I->SetMachineOperandReg(1, EvenSrcReg); else if (MI->getOpcode() == V8::FpNEGD)
DEBUG(std::cerr << "FPMover: the modified instr is: " << *I); MI->setOpcode(V8::FNEGS);
// Insert copy for the other half of the double: else if (MI->getOpcode() == V8::FpABSD)
MI->setOpcode(V8::FABSS);
else
assert(0 && "Unknown opcode!");
MI->SetMachineOperandReg(0, EvenDestReg);
MI->SetMachineOperandReg(1, EvenSrcReg);
DEBUG(std::cerr << "FPMover: the modified instr is: " << *MI);
// Insert copy for the other half of the double.
if (DestDReg != SrcDReg) {
MI = BuildMI(MBB, I, V8::FMOVS, 1, OddDestReg).addReg(OddSrcReg); MI = BuildMI(MBB, I, V8::FMOVS, 1, OddDestReg).addReg(OddSrcReg);
DEBUG(std::cerr << "FPMover: the inserted instr is: " << *MI); DEBUG(std::cerr << "FPMover: the inserted instr is: " << *MI);
++NumFpDs;
} else {
MBB.erase(MI);
++NoopFpDs;
} }
Changed = true; ++NumFpDs;
} }
} }
return Changed; return Changed;

12
lib/Target/Sparc/SparcInstrInfo.td
View File

@ -118,8 +118,17 @@ def IMPLICIT_DEF_FP : Pseudo<(ops FPRegs:$dst), "!IMPLICIT_DEF $dst",
[(set FPRegs:$dst, (undef))]>; [(set FPRegs:$dst, (undef))]>;
def IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst", def IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst",
[(set DFPRegs:$dst, (undef))]>; [(set DFPRegs:$dst, (undef))]>;
// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
// fpmover pass.
def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
"!FpMOVD", []>; // pseudo 64-bit double move "!FpMOVD $src, $dst", []>; // pseudo 64-bit double move
def FpNEGD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
"!FpNEGD $src, $dst",
[(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
def FpABSD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
"!FpABSD $src, $dst",
[(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
// scheduler into a branch sequence. This has to handle all permutations of // scheduler into a branch sequence. This has to handle all permutations of
@ -624,7 +633,6 @@ def FABSS : F3_3<2, 0b110100, 0b000001001,
(ops FPRegs:$dst, FPRegs:$src), (ops FPRegs:$dst, FPRegs:$src),
"fabss $src, $dst", "fabss $src, $dst",
[(set FPRegs:$dst, (fabs FPRegs:$src))]>; [(set FPRegs:$dst, (fabs FPRegs:$src))]>;
// FIXME: ADD FNEGD/FABSD pseudo instructions.
// Floating-point Square Root Instructions, p.145 // Floating-point Square Root Instructions, p.145

42
lib/Target/SparcV8/FPMover.cpp
View File

@ -84,27 +84,39 @@ bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
bool Changed = false; bool Changed = false;
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) { for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
MachineInstr *MI = I++; MachineInstr *MI = I++;
if (MI->getOpcode() == V8::FpMOVD) { if (MI->getOpcode() == V8::FpMOVD || MI->getOpcode() == V8::FpABSD ||
MI->getOpcode() == V8::FpNEGD) {
Changed = true;
unsigned DestDReg = MI->getOperand(0).getReg(); unsigned DestDReg = MI->getOperand(0).getReg();
unsigned SrcDReg = MI->getOperand(1).getReg(); unsigned SrcDReg = MI->getOperand(1).getReg();
if (DestDReg != SrcDReg || MI->getOpcode() != V8::FpMOVD) { if (DestDReg == SrcDReg && MI->getOpcode() == V8::FpMOVD) {
unsigned EvenSrcReg = 0, OddSrcReg = 0, EvenDestReg = 0, OddDestReg = 0; MBB.erase(MI); // Eliminate the noop copy.
getDoubleRegPair(DestDReg, EvenDestReg, OddDestReg); ++NoopFpDs;
getDoubleRegPair(SrcDReg, EvenSrcReg, OddSrcReg); continue;
}
unsigned EvenSrcReg = 0, OddSrcReg = 0, EvenDestReg = 0, OddDestReg = 0;
getDoubleRegPair(DestDReg, EvenDestReg, OddDestReg);
getDoubleRegPair(SrcDReg, EvenSrcReg, OddSrcReg);
I->setOpcode(V8::FMOVS); if (MI->getOpcode() == V8::FpMOVD)
I->SetMachineOperandReg(0, EvenDestReg); MI->setOpcode(V8::FMOVS);
I->SetMachineOperandReg(1, EvenSrcReg); else if (MI->getOpcode() == V8::FpNEGD)
DEBUG(std::cerr << "FPMover: the modified instr is: " << *I); MI->setOpcode(V8::FNEGS);
// Insert copy for the other half of the double: else if (MI->getOpcode() == V8::FpABSD)
MI->setOpcode(V8::FABSS);
else
assert(0 && "Unknown opcode!");
MI->SetMachineOperandReg(0, EvenDestReg);
MI->SetMachineOperandReg(1, EvenSrcReg);
DEBUG(std::cerr << "FPMover: the modified instr is: " << *MI);
// Insert copy for the other half of the double.
if (DestDReg != SrcDReg) {
MI = BuildMI(MBB, I, V8::FMOVS, 1, OddDestReg).addReg(OddSrcReg); MI = BuildMI(MBB, I, V8::FMOVS, 1, OddDestReg).addReg(OddSrcReg);
DEBUG(std::cerr << "FPMover: the inserted instr is: " << *MI); DEBUG(std::cerr << "FPMover: the inserted instr is: " << *MI);
++NumFpDs;
} else {
MBB.erase(MI);
++NoopFpDs;
} }
Changed = true; ++NumFpDs;
} }
} }
return Changed; return Changed;

12
lib/Target/SparcV8/SparcV8InstrInfo.td
View File

@ -118,8 +118,17 @@ def IMPLICIT_DEF_FP : Pseudo<(ops FPRegs:$dst), "!IMPLICIT_DEF $dst",
[(set FPRegs:$dst, (undef))]>; [(set FPRegs:$dst, (undef))]>;
def IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst", def IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst",
[(set DFPRegs:$dst, (undef))]>; [(set DFPRegs:$dst, (undef))]>;
// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
// fpmover pass.
def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
"!FpMOVD", []>; // pseudo 64-bit double move "!FpMOVD $src, $dst", []>; // pseudo 64-bit double move
def FpNEGD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
"!FpNEGD $src, $dst",
[(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
def FpABSD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
"!FpABSD $src, $dst",
[(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
// scheduler into a branch sequence. This has to handle all permutations of // scheduler into a branch sequence. This has to handle all permutations of
@ -624,7 +633,6 @@ def FABSS : F3_3<2, 0b110100, 0b000001001,
(ops FPRegs:$dst, FPRegs:$src), (ops FPRegs:$dst, FPRegs:$src),
"fabss $src, $dst", "fabss $src, $dst",
[(set FPRegs:$dst, (fabs FPRegs:$src))]>; [(set FPRegs:$dst, (fabs FPRegs:$src))]>;
// FIXME: ADD FNEGD/FABSD pseudo instructions.
// Floating-point Square Root Instructions, p.145 // Floating-point Square Root Instructions, p.145