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Thumb2 assembly parsing and encoding for MSR/MRS.
Fix a bug in handling default flags for both ARM and Thumb encodings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139721 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
97f50f3870
commit
bf841cf336
@ -3507,33 +3507,22 @@ defm t2STC : T2LdStCop<0b1111, 0, "stc">;
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//===----------------------------------------------------------------------===//
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// Move between special register and ARM core register -- for disassembly only
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//
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class T2SpecialReg<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
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dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: T2I<oops, iops, itin, opc, asm, pattern> {
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let Inst{31-20} = op31_20{11-0};
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let Inst{15-14} = op15_14{1-0};
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let Inst{13} = 0b0;
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let Inst{12} = op12{0};
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let Inst{7-0} = 0;
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}
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class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
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dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
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// Move to ARM core register from Special Register
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def t2MRS : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", []> {
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bits<4> Rd;
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let Inst{31-12} = 0b11110011111011111000;
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let Inst{11-8} = Rd;
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let Inst{19-16} = 0b1111;
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let Inst{7-0} = 0b0000;
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}
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def t2MRS : T2MRS<0b111100111110, 0b10, 0,
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(outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
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[/* For disassembly only; pattern left blank */]>;
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def t2MRSsys : T2MRS<0b111100111111, 0b10, 0,
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(outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
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[/* For disassembly only; pattern left blank */]>;
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def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS GPR:$Rd, pred:$p)>;
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def t2MRSsys:T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", []> {
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bits<4> Rd;
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let Inst{31-12} = 0b11110011111111111000;
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let Inst{11-8} = Rd;
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let Inst{7-0} = 0b0000;
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}
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// Move from ARM core register to Special Register
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//
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@ -3541,15 +3530,16 @@ def t2MRSsys : T2MRS<0b111100111111, 0b10, 0,
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// same and the assembly parser has no way to distinguish between them. The mask
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// operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
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// the mask with the fields to be accessed in the special register.
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def t2MSR : T2SpecialReg<0b111100111000 /* op31-20 */, 0b10 /* op15-14 */,
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0 /* op12 */, (outs), (ins msr_mask:$mask, rGPR:$Rn),
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NoItinerary, "msr", "\t$mask, $Rn",
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[/* For disassembly only; pattern left blank */]> {
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def t2MSR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
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NoItinerary, "msr", "\t$mask, $Rn", []> {
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bits<5> mask;
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bits<4> Rn;
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let Inst{19-16} = Rn;
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let Inst{31-21} = 0b11110011100;
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let Inst{20} = mask{4}; // R Bit
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let Inst{19-16} = Rn;
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let Inst{15-12} = 0b1000;
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let Inst{11-8} = mask{3-0};
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let Inst{7-0} = 0;
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}
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//===----------------------------------------------------------------------===//
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@ -2077,7 +2077,7 @@ parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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if (!Flags.empty())
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return MatchOperand_NoMatch;
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else
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FlagsVal = 0; // No flag
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FlagsVal = 8; // No flag
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}
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} else if (SpecReg == "cpsr" || SpecReg == "spsr") {
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if (Flags == "all") // cpsr_all is an alias for cpsr_fc
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@ -838,7 +838,7 @@ Lforward:
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msr SPSR_fsxc, #5
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msr cpsr_fsxc, #5
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@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x29,0xe3]
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@ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
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@ CHECK: msr APSR_g, #5 @ encoding: [0x05,0xf0,0x24,0xe3]
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@ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
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@ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
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@ -868,7 +868,7 @@ Lforward:
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msr SPSR_fsxc, r0
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msr cpsr_fsxc, r0
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@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1]
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@ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
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@ CHECK: msr APSR_g, r0 @ encoding: [0x00,0xf0,0x24,0xe1]
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@ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
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@ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
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@ -1062,6 +1062,52 @@ _func:
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@ CHECK: mrrc2 p7, #1, r5, r4, c1 @ encoding: [0x54,0xfc,0x11,0x57]
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@------------------------------------------------------------------------------
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@ MRS
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@------------------------------------------------------------------------------
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mrs r8, apsr
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mrs r8, cpsr
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mrs r8, spsr
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@ CHECK: mrs r8, apsr @ encoding: [0xef,0xf3,0x00,0x88]
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@ CHECK: mrs r8, apsr @ encoding: [0xef,0xf3,0x00,0x88]
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@ CHECK: mrs r8, spsr @ encoding: [0xff,0xf3,0x00,0x88]
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@------------------------------------------------------------------------------
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@ MSR
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@------------------------------------------------------------------------------
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msr apsr, r1
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msr apsr_g, r2
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msr apsr_nzcvq, r3
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msr APSR_nzcvq, r4
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msr apsr_nzcvqg, r5
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msr cpsr_fc, r6
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msr cpsr_c, r7
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msr cpsr_x, r8
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msr cpsr_fc, r9
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msr cpsr_all, r11
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msr cpsr_fsx, r12
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msr spsr_fc, r0
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msr SPSR_fsxc, r5
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msr cpsr_fsxc, r8
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@ CHECK: msr APSR_nzcvq, r1 @ encoding: [0x81,0xf3,0x00,0x88]
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@ CHECK: msr APSR_g, r2 @ encoding: [0x82,0xf3,0x00,0x84]
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@ CHECK: msr APSR_nzcvq, r3 @ encoding: [0x83,0xf3,0x00,0x88]
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@ CHECK: msr APSR_nzcvq, r4 @ encoding: [0x84,0xf3,0x00,0x88]
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@ CHECK: msr APSR_nzcvqg, r5 @ encoding: [0x85,0xf3,0x00,0x8c]
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@ CHECK: msr CPSR_fc, r6 @ encoding: [0x86,0xf3,0x00,0x89]
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@ CHECK: msr CPSR_c, r7 @ encoding: [0x87,0xf3,0x00,0x81]
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@ CHECK: msr CPSR_x, r8 @ encoding: [0x88,0xf3,0x00,0x82]
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@ CHECK: msr CPSR_fc, r9 @ encoding: [0x89,0xf3,0x00,0x89]
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@ CHECK: msr CPSR_fc, r11 @ encoding: [0x8b,0xf3,0x00,0x89]
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@ CHECK: msr CPSR_fsx, r12 @ encoding: [0x8c,0xf3,0x00,0x8e]
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@ CHECK: msr SPSR_fc, r0 @ encoding: [0x90,0xf3,0x00,0x89]
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@ CHECK: msr SPSR_fsxc, r5 @ encoding: [0x95,0xf3,0x00,0x8f]
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@ CHECK: msr CPSR_fsxc, r8 @ encoding: [0x88,0xf3,0x00,0x8f]
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@------------------------------------------------------------------------------
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@ IT
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@------------------------------------------------------------------------------
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