diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 8715657ad5e..e0810c358f2 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -665,12 +665,14 @@ bool ARMBaseInstrInfo::isPredicable(const MachineInstr &MI) const {
   const ARMFunctionInfo *AFI =
       MI.getParent()->getParent()->getInfo<ARMFunctionInfo>();
 
+  // Neon instructions in Thumb2 IT blocks are deprecated, see ARMARM.
+  // In their ARM encoding, they can't be encoded in a conditional form.
+  if ((MI.getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
+    return false;
+
   if (AFI->isThumb2Function()) {
     if (getSubtarget().restrictIT())
       return isV8EligibleForIT(&MI);
-  } else { // non-Thumb
-    if ((MI.getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
-      return false;
   }
 
   return true;
diff --git a/test/CodeGen/ARM/2012-08-30-select.ll b/test/CodeGen/ARM/2012-08-30-select.ll
index dbedad2637b..97b732beb4d 100644
--- a/test/CodeGen/ARM/2012-08-30-select.ll
+++ b/test/CodeGen/ARM/2012-08-30-select.ll
@@ -2,10 +2,9 @@
 ; rdar://12201387
 
 ;CHECK-LABEL: select_s_v_v:
-;CHECK: itee  ne
-;CHECK-NEXT: vmovne.i32
-;CHECK-NEXT: vmoveq
-;CHECK-NEXT: vmoveq
+;CHECK: vmov
+;CHECK-NEXT: vmov
+;CHECK: vmov.i32
 ;CHECK: bx
 define <16 x i8> @select_s_v_v(<16 x i8> %vec, i32 %avail) {
 entry:
diff --git a/test/CodeGen/ARM/vector-promotion.ll b/test/CodeGen/ARM/vector-promotion.ll
index 1dabee38608..9e2b35fe825 100644
--- a/test/CodeGen/ARM/vector-promotion.ll
+++ b/test/CodeGen/ARM/vector-promotion.ll
@@ -53,8 +53,8 @@ define void @unsupportedInstructionForPromotion(<2 x i32>* %addr1, i32 %in2, i1*
 ; IR-BOTH: ret
 ;
 ; ASM-LABEL: unsupportedChainInDifferentBBs:
-; ASM: vldrne [[LOAD:d[0-9]+]], [r0]
-; ASM: vmovne.32 {{r[0-9]+}}, [[LOAD]]
+; ASM: vldr [[LOAD:d[0-9]+]], [r0]
+; ASM: vmov.32 {{r[0-9]+}}, [[LOAD]]
 ; ASM: bx
 define void @unsupportedChainInDifferentBBs(<2 x i32>* %addr1, i32* %dest, i1 %bool) {
 bb1:
diff --git a/test/CodeGen/Thumb2/ifcvt-neon-deprecated.mir b/test/CodeGen/Thumb2/ifcvt-neon-deprecated.mir
new file mode 100644
index 00000000000..a44604372e6
--- /dev/null
+++ b/test/CodeGen/Thumb2/ifcvt-neon-deprecated.mir
@@ -0,0 +1,54 @@
+# RUN: llc -mtriple=thumbv7 -start-before=if-converter -o - %s | FileCheck %s
+---
+name:            NeonVdupMul
+body:             |
+  bb.0:
+    successors: %bb.2, %bb.1
+    liveins: %d0, %r0, %r1
+
+    t2CMPri killed %r1, 0, 14, _, implicit-def %cpsr
+    t2Bcc %bb.2, 0, killed %cpsr
+
+  bb.1:
+    liveins: %d0, %r0
+
+    %d16 = VDUP32d killed %r0, 14, _
+    ; Verify that the neon instructions haven't been conditionalized:
+    ; CHECK-LABEL: NeonVdupMul
+    ; CHECK: vdup.32
+    ; CHECK: vmul.i32
+    %d0 = VMULv2i32 killed %d16, killed %d0, 14, _
+
+  bb.2:
+    liveins: %d0
+
+    tBX_RET 14, _, implicit %d0
+
+...
+---
+name:            NeonVmovVfpLdr
+body:             |
+  bb.0.entry:
+    successors: %bb.1, %bb.2
+    liveins: %r0, %r1
+
+    t2CMPri killed %r1, 0, 14, _, implicit-def %cpsr
+    t2Bcc %bb.2, 1, killed %cpsr
+
+  bb.1:
+    %d0 = VMOVv2i32 0, 14, _
+    tBX_RET 14, _, implicit %d0
+
+  bb.2:
+    liveins: %r0
+
+    %d0 = VLDRD killed %r0, 0, 14, _
+    ; Verify that the neon instruction VMOVv2i32 hasn't been conditionalized,
+    ; but the VLDR instruction that is available both in the VFP and Advanced
+    ; SIMD extensions has.
+    ; CHECK-LABEL: NeonVmovVfpLdr
+    ; CHECK-DAG: vmov.i32 d0, #0x0
+    ; CHECK-DAG: vldr{{ne|eq}} d0, [r0]
+    tBX_RET 14, _, implicit %d0
+
+...
diff --git a/test/CodeGen/Thumb2/ifcvt-neon.ll b/test/CodeGen/Thumb2/ifcvt-neon.ll
deleted file mode 100644
index 83c0b601aba..00000000000
--- a/test/CodeGen/Thumb2/ifcvt-neon.ll
+++ /dev/null
@@ -1,29 +0,0 @@
-; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
-; rdar://7368193
-
-@a = common global float 0.000000e+00             ; <float*> [#uses=2]
-@b = common global float 0.000000e+00             ; <float*> [#uses=1]
-
-define float @t(i32 %c) nounwind {
-entry:
-  %0 = icmp sgt i32 %c, 1                         ; <i1> [#uses=1]
-  %1 = load float, float* @a, align 4                    ; <float> [#uses=2]
-  %2 = load float, float* @b, align 4                    ; <float> [#uses=2]
-  br i1 %0, label %bb, label %bb1
-
-bb:                                               ; preds = %entry
-; CHECK:      vsub.f32
-; CHECK-NEXT: vadd.f32
-; CHECK:      it gt
-  %3 = fadd float %1, %2                          ; <float> [#uses=1]
-  br label %bb2
-
-bb1:                                              ; preds = %entry
-  %4 = fsub float %1, %2                          ; <float> [#uses=1]
-  br label %bb2
-
-bb2:                                              ; preds = %bb1, %bb
-  %storemerge = phi float [ %4, %bb1 ], [ %3, %bb ] ; <float> [#uses=2]
-  store float %storemerge, float* @a
-  ret float %storemerge
-}