mirror of
https://github.com/RPCS3/llvm.git
synced 2024-12-13 06:39:12 +00:00
Use getClassB for load and store; we don't want to abort when we
try to load or store through a bool*. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7195 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
1d2ba44224
commit
bfedb912cd
@ -1433,7 +1433,7 @@ void ISel::visitLoadInst(LoadInst &I) {
|
||||
unsigned SrcAddrReg = getReg(I.getOperand(0));
|
||||
unsigned DestReg = getReg(I);
|
||||
|
||||
unsigned Class = getClass(I.getType());
|
||||
unsigned Class = getClassB(I.getType());
|
||||
switch (Class) {
|
||||
case cFP: {
|
||||
MachineBasicBlock::iterator MBBI = BB->end();
|
||||
@ -1533,7 +1533,7 @@ void ISel::visitStoreInst(StoreInst &I) {
|
||||
unsigned ValReg = getReg(I.getOperand(0));
|
||||
unsigned AddressReg = getReg(I.getOperand(1));
|
||||
|
||||
unsigned Class = getClass(I.getOperand(0)->getType());
|
||||
unsigned Class = getClassB(I.getOperand(0)->getType());
|
||||
switch (Class) {
|
||||
case cLong:
|
||||
if (isLittleEndian) {
|
||||
|
@ -1433,7 +1433,7 @@ void ISel::visitLoadInst(LoadInst &I) {
|
||||
unsigned SrcAddrReg = getReg(I.getOperand(0));
|
||||
unsigned DestReg = getReg(I);
|
||||
|
||||
unsigned Class = getClass(I.getType());
|
||||
unsigned Class = getClassB(I.getType());
|
||||
switch (Class) {
|
||||
case cFP: {
|
||||
MachineBasicBlock::iterator MBBI = BB->end();
|
||||
@ -1533,7 +1533,7 @@ void ISel::visitStoreInst(StoreInst &I) {
|
||||
unsigned ValReg = getReg(I.getOperand(0));
|
||||
unsigned AddressReg = getReg(I.getOperand(1));
|
||||
|
||||
unsigned Class = getClass(I.getOperand(0)->getType());
|
||||
unsigned Class = getClassB(I.getOperand(0)->getType());
|
||||
switch (Class) {
|
||||
case cLong:
|
||||
if (isLittleEndian) {
|
||||
|
Loading…
Reference in New Issue
Block a user