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Replace dregsingle operand modifier with explicit escaped curly brackets.

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For other VLDn and VSTn operations, we need to list the multiple registers
explicitly anyway, so there's no point in special-casing this one usage.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78109 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2009-08-04 21:39:33 +00:00
parent ad5312ad70
commit c00479253b
2 changed files with 2 additions and 4 deletions
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4
lib/Target/ARM/ARMInstrNEON.td
View File

@ -142,7 +142,7 @@ def VSTRQ : NI<(outs), (ins QPR:$src, GPR:$addr),
// VLD1 : Vector Load (multiple single elements)
class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
: NLdSt<(outs DPR:$dst), (ins addrmode6:$addr),
!strconcat(OpcodeStr, "\t${dst:dregsingle}, $addr"),
!strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"),
[(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
class VLD1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
: NLdSt<(outs QPR:$dst), (ins addrmode6:$addr),
@ -164,7 +164,7 @@ def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1i>;
// VST1 : Vector Store (multiple single elements)
class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
: NLdSt<(outs), (ins addrmode6:$addr, DPR:$src),
!strconcat(OpcodeStr, "\t${src:dregsingle}, $addr"),
!strconcat(OpcodeStr, "\t\\{$src\\}, $addr"),
[(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
class VST1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
: NLdSt<(outs), (ins addrmode6:$addr, QPR:$src),

2
lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
View File

@ -348,8 +348,6 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
O << '{'
<< TRI->getAsmName(DRegLo) << ',' << TRI->getAsmName(DRegHi)
<< '}';
} else if (Modifier && strcmp(Modifier, "dregsingle") == 0) {
O << '{' << TRI->getAsmName(Reg) << '}';
} else {
O << TRI->getAsmName(Reg);
}