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Schedule high latency instructions for latency reduction even if they are not vfp / NEON instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105060 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2010-05-28 23:25:23 +00:00
parent 2f05cc06a2
commit c10f5434b4
1 changed files with 19 additions and 1 deletions
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20
lib/Target/ARM/ARMISelLowering.cpp
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@ -605,11 +605,29 @@ unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
}
Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
unsigned NumVals = N->getNumValues();
if (!NumVals)
return Sched::RegPressure;
for (unsigned i = 0; i != NumVals; ++i) {
EVT VT = N->getValueType(i);
if (VT.isFloatingPoint() || VT.isVector())
return Sched::Latency;
}
if (!N->isMachineOpcode())
return Sched::RegPressure;
// Load are scheduled for latency even if there instruction itinerary
// is not available.
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
if (TID.mayLoad())
return Sched::Latency;
const InstrItineraryData &Itins = getTargetMachine().getInstrItineraryData();
if (!Itins.isEmpty() && Itins.getStageLatency(TID.getSchedClass()) > 2)
return Sched::Latency;
return Sched::RegPressure;
}