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ARM: fix more cases where predication may or may not be allowed
Unfortunately this addresses two issues (by the time I'd disentangled the logic it wasn't worth putting it back to half-broken): + Coprocessor instructions should all be predicable in Thumb mode. + BKPT should never be predicable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184965 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
parent
c1a91dd97b
commit
c19bd32136
@ -1230,8 +1230,9 @@ class T2JTI<dag oops, dag iops, InstrItinClass itin,
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: Thumb2XI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
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// Move to/from coprocessor instructions
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class T2Cop<bits<4> opc, dag oops, dag iops, string asm, list<dag> pattern>
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: T2XI <oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2]> {
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class T2Cop<bits<4> opc, dag oops, dag iops, string opcstr, string asm,
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list<dag> pattern>
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: T2I <oops, iops, NoItinerary, opcstr, asm, pattern>, Requires<[IsThumb2]> {
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let Inst{31-28} = opc;
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}
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@ -1730,12 +1730,13 @@ def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
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// The 16-bit operand $val can be used by a debugger to store more information
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// about the breakpoint.
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def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
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"bkpt", "\t$val", []>, Requires<[IsARM]> {
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def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
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"bkpt", "\t$val", []>, Requires<[IsARM]> {
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bits<16> val;
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let Inst{3-0} = val{3-0};
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let Inst{19-8} = val{15-4};
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let Inst{27-20} = 0b00010010;
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let Inst{31-28} = 0xe; // AL
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let Inst{7-4} = 0b0111;
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}
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@ -3825,8 +3825,7 @@ def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
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class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
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list<dag> pattern>
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: T2Cop<Op, oops, iops,
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!strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
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: T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
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pattern> {
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let Inst{27-24} = 0b1110;
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let Inst{20} = direction;
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@ -3851,7 +3850,7 @@ class t2MovRRCopro<bits<4> Op, string opc, bit direction,
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list<dag> pattern = []>
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: T2Cop<Op, (outs),
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(ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
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!strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
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opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
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let Inst{27-24} = 0b1100;
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let Inst{23-21} = 0b010;
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let Inst{20} = direction;
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@ -3876,32 +3875,32 @@ def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
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c_imm:$CRm, imm0_7:$opc2),
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[(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
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imm:$CRm, imm:$opc2)]>;
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def : t2InstAlias<"mcr $cop, $opc1, $Rt, $CRn, $CRm",
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def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
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(t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
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c_imm:$CRm, 0)>;
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c_imm:$CRm, 0, pred:$p)>;
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def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
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(outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
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c_imm:$CRm, imm0_7:$opc2),
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[(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
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imm:$CRm, imm:$opc2)]>;
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def : t2InstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm",
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def : t2InstAlias<"mcr2${p} $cop, $opc1, $Rt, $CRn, $CRm",
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(t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
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c_imm:$CRm, 0)>;
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c_imm:$CRm, 0, pred:$p)>;
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/* from coprocessor to ARM core register */
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def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
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(outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
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c_imm:$CRm, imm0_7:$opc2), []>;
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def : t2InstAlias<"mrc $cop, $opc1, $Rt, $CRn, $CRm",
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def : t2InstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
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(t2MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
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c_imm:$CRm, 0)>;
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c_imm:$CRm, 0, pred:$p)>;
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def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
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(outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
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c_imm:$CRm, imm0_7:$opc2), []>;
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def : t2InstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
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def : t2InstAlias<"mrc2${p} $cop, $opc1, $Rt, $CRn, $CRm",
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(t2MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
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c_imm:$CRm, 0)>;
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c_imm:$CRm, 0, pred:$p)>;
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def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
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(t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
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@ -3928,7 +3927,7 @@ def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
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def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
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c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
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"cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
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"cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
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[(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
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imm:$CRm, imm:$opc2)]> {
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let Inst{27-24} = 0b1110;
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@ -3951,7 +3950,7 @@ def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
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def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
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c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
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"cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
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"cdp2", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
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[(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
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imm:$CRm, imm:$opc2)]> {
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let Inst{27-24} = 0b1110;
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@ -4966,28 +4966,26 @@ getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
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} else
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CanAcceptCarrySet = false;
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if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "cps" ||
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Mnemonic == "mcr2" || Mnemonic == "it" || Mnemonic == "mcrr2" ||
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Mnemonic == "cbz" || Mnemonic == "cdp2" || Mnemonic == "trap" ||
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Mnemonic == "mrc2" || Mnemonic == "mrrc2" || Mnemonic == "setend" ||
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((Mnemonic == "clrex" || Mnemonic == "dmb" || Mnemonic == "dsb" ||
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Mnemonic == "isb") && !isThumb()) ||
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(Mnemonic == "nop" && isThumbOne()) ||
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((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
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Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
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Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
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((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
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!isThumb()) ||
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Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
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if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
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Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
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Mnemonic == "trap" || Mnemonic == "setend" ||
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Mnemonic.startswith("cps")) {
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// These mnemonics are never predicable
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CanAcceptPredicationCode = false;
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} else if (!isThumb()) {
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// Some instructions are only predicable in Thumb mode
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CanAcceptPredicationCode
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= Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
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Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
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Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
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Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
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Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
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Mnemonic != "stc2" && Mnemonic != "stc2l" &&
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!Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
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} else if (isThumbOne()) {
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CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
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} else
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CanAcceptPredicationCode = true;
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if (isThumb()) {
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if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
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Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
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CanAcceptPredicationCode = false;
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}
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}
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bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
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@ -465,6 +465,8 @@ Lforward:
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@ CHECK: cdp2 p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xfe]
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@ CHECK: cdp2 p10, #0, c6, c12, c0, #7 @ encoding: [0xe0,0x6a,0x0c,0xfe]
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cdpne p7, #1, c1, c1, c1, #4
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@ CHECK: cdpne p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0x1e]
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@------------------------------------------------------------------------------
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@ CLREX
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@ -969,6 +971,9 @@ Lforward:
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@ CHECK: mcr p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xee]
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@ CHECK: mcr2 p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xfe]
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mcrls p7, #1, r5, c1, c1, #4
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@ CHECK: mcrls p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0x9e]
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@------------------------------------------------------------------------------
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@ MCRR/MCRR2
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@------------------------------------------------------------------------------
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@ -978,6 +983,8 @@ Lforward:
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@ CHECK: mcrr p7, #15, r5, r4, c1 @ encoding: [0xf1,0x57,0x44,0xec]
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@ CHECK: mcrr2 p7, #15, r5, r4, c1 @ encoding: [0xf1,0x57,0x44,0xfc]
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mcrrgt p7, #15, r5, r4, c1
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@ CHECK: mcrrgt p7, #15, r5, r4, c1 @ encoding: [0xf1,0x57,0x44,0xcc]
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@------------------------------------------------------------------------------
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@ MLA
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@ -1081,6 +1088,9 @@ Lforward:
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@ CHECK: mrc2 p10, #7, apsr_nzcv, c15, c0, #1 @ encoding: [0x30,0xfa,0xff,0xfe]
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@ CHECK: mrc2 p10, #7, pc, c15, c0, #1 @ encoding: [0x30,0xfa,0xff,0xfe]
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mrceq p15, #7, pc, c15, c6, #6
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@ CHECK: mrceq p15, #7, pc, c15, c6, #6 @ encoding: [0xd6,0xff,0xff,0x0e]
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@------------------------------------------------------------------------------
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@ MRRC/MRRC2
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@------------------------------------------------------------------------------
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@ -1090,6 +1100,8 @@ Lforward:
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@ CHECK: mrrc p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xec]
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@ CHECK: mrrc2 p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xfc]
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mrrclo p7, #1, r5, r4, c1
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@ CHECK: mrrclo p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0x3c]
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@------------------------------------------------------------------------------
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@ MRS
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@ -393,3 +393,17 @@
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@ CHECK-ERRORS: error: instruction 'dmb' is not predicable, but condition code specified
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@ CHECK-ERRORS: error: instruction 'dsb' is not predicable, but condition code specified
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@ CHECK-ERRORS: error: instruction 'isb' is not predicable, but condition code specified
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mcr2le p7, #1, r5, c1, c1, #4
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mcrr2ne p7, #15, r5, r4, c1
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mrc2lo p14, #0, r1, c1, c2, #4
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mrrc2lo p7, #1, r5, r4, c1
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cdp2hi p10, #0, c6, c12, c0, #7
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@ CHECK-ERRORS: error: instruction 'mcr2' is not predicable, but condition code specified
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@ CHECK-ERRORS: error: instruction 'mcrr2' is not predicable, but condition code specified
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@ CHECK-ERRORS: error: instruction 'mrc2' is not predicable, but condition code specified
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@ CHECK-ERRORS: error: instruction 'mrrc2' is not predicable, but condition code specified
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@ CHECK-ERRORS: error: instruction 'cdp2' is not predicable, but condition code specified
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bkpteq #7
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@ CHECK-ERRORS: error: instruction 'bkpt' is not predicable, but condition code specified
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@ -17,3 +17,38 @@
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@ CHECK-NEXT: dmble sy
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@ CHECK-NEXT: dsbgt sy
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@ CHECK-NEXT: isble sy
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itt gt
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cdpgt p7, #1, c1, c1, c1, #4
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cdp2gt p7, #1, c1, c1, c1, #4
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@ CHECK: itt gt
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@ CHECK-NEXT: cdpgt p7, #1, c1, c1, c1, #4
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@ CHECK-NEXT: cdp2gt p7, #1, c1, c1, c1, #4
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itt ne
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mcrne p0, #0, r0, c0, c0, #0
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mcr2ne p0, #0, r0, c0, c0, #0
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@ CHECK: itt ne
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@ CHECK-NEXT: mcrne p0, #0, r0, c0, c0, #0
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@ CHECK-NEXT: mcr2ne p0, #0, r0, c0, c0, #0
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ite le
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mcrrle p7, #15, r5, r4, c1
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mcrr2gt p7, #15, r5, r4, c1
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@ CHECK: ite le
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@ CHECK-NEXT: mcrrle p7, #15, r5, r4, c1
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@ CHECK-NEXT: mcrr2gt p7, #15, r5, r4, c1
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ite eq
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mrceq p11, #1, r1, c2, c2
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mrc2ne p12, #3, r3, c3, c4
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@ CHECK: ite eq
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@ CHECK-NEXT: mrceq p11, #1, r1, c2, c2
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@ CHECK-NEXT: mrc2ne p12, #3, r3, c3, c4
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itt lo
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mrrclo p7, #1, r5, r4, c1
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mrrc2lo p7, #1, r5, r4, c1
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@ CHECK: itt lo
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@ CHECK-NEXT: mrrclo p7, #1, r5, r4, c1
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@ CHECK-NEXT: mrrc2lo p7, #1, r5, r4, c1
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@ -47,3 +47,7 @@
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isb #16
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@ CHECK-ERRORS: error: immediate value out of range
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@ CHECK-ERRORS: error: immediate value out of range
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itt eq
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bkpteq #1
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@ CHECK-ERRORS: error: instruction 'bkpt' is not predicable, but condition code specified
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