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ms inline asm: Don't add x86 segment registers to the clobber list.
Clang tries to check the clobber list but doesn't list segment registers in its x86 register list. This fixes PR20343. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213303 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -164,6 +164,9 @@ public:
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unsigned &ErrorInfo,
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bool MatchingInlineAsm) = 0;
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/// Allows targets to let registers opt out of clobber lists.
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virtual bool OmitRegisterFromClobberLists(unsigned RegNo) { return false; }
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/// Allow a target to add special case operand matching for things that
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/// tblgen doesn't/can't handle effectively. For example, literal
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/// immediates on ARM. TableGen expects a token operand, but the parser
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@ -4510,7 +4510,8 @@ bool AsmParser::parseMSInlineAsm(
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continue;
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// Register operand.
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if (Operand.isReg() && !Operand.needAddressOf()) {
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if (Operand.isReg() && !Operand.needAddressOf() &&
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!getTargetParser().OmitRegisterFromClobberLists(Operand.getReg())) {
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unsigned NumDefs = Desc.getNumDefs();
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// Clobber.
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if (NumDefs && Operand.getMCOperandNum() < NumDefs)
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@ -696,6 +696,8 @@ private:
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unsigned &ErrorInfo,
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bool MatchingInlineAsm) override;
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virtual bool OmitRegisterFromClobberLists(unsigned RegNo) override;
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/// doSrcDstMatch - Returns true if operands are matching in their
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/// word size (%si and %di, %esi and %edi, etc.). Order depends on
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/// the parsing mode (Intel vs. AT&T).
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@ -2520,6 +2522,9 @@ bool X86AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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return true;
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}
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bool X86AsmParser::OmitRegisterFromClobberLists(unsigned RegNo) {
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return X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo);
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}
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bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
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StringRef IDVal = DirectiveID.getIdentifier();
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