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[ARM] GlobalISel: Legalize s8 and s16 G_(S|U)DIV
We have to widen the operands to 32 bits and then we can either use hardware division if it is available or lower to a libcall otherwise. At the moment it is not enough to set the Legalizer action to WidenScalar, since for libcalls it won't know what to do (it won't be able to find what size to widen to, because it will find Libcall and not Legal for 32 bits). To hack around this limitation, we request Custom lowering, and as part of that we widen first and then we run another legalizeInstrStep on the widened DIV. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301166 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Diana Picus
parent
8e5f1d4de2
commit
c1f12989a6
@ -13,6 +13,8 @@
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#include "ARMLegalizerInfo.h"
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#include "ARMSubtarget.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Type.h"
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@ -48,6 +50,11 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
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setAction({Op, Ty}, Legal);
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for (unsigned Op : {G_SDIV, G_UDIV}) {
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for (auto Ty : {s8, s16})
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// FIXME: We need WidenScalar here, but in the case of targets with
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// software division we'll also need Libcall afterwards. Treat as Custom
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// until we have better support for chaining legalization actions.
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setAction({Op, Ty}, Custom);
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if (ST.hasDivideInARMMode())
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setAction({Op, s32}, Legal);
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else
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@ -82,3 +89,48 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
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computeTables();
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}
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bool ARMLegalizerInfo::legalizeCustom(MachineInstr &MI,
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MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const {
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using namespace TargetOpcode;
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switch (MI.getOpcode()) {
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default:
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return false;
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case G_SDIV:
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case G_UDIV: {
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LLT Ty = MRI.getType(MI.getOperand(0).getReg());
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if (Ty != LLT::scalar(16) && Ty != LLT::scalar(8))
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return false;
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// We need to widen to 32 bits and then maybe, if the target requires,
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// transform into a libcall.
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LegalizerHelper Helper(MIRBuilder.getMF());
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MachineInstr *NewMI = nullptr;
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Helper.MIRBuilder.recordInsertions([&](MachineInstr *MI) {
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// Store the new, 32-bit div instruction.
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if (MI->getOpcode() == G_SDIV || MI->getOpcode() == G_UDIV)
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NewMI = MI;
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});
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auto Result = Helper.widenScalar(MI, 0, LLT::scalar(32));
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Helper.MIRBuilder.stopRecordingInsertions();
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if (Result == LegalizerHelper::UnableToLegalize) {
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return false;
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}
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assert(NewMI && "Couldn't find widened instruction");
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assert((NewMI->getOpcode() == G_SDIV || NewMI->getOpcode() == G_UDIV) &&
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"Unexpected widened instruction");
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assert(MRI.getType(NewMI->getOperand(0).getReg()).getSizeInBits() == 32 &&
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"Unexpected type for the widened instruction");
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Result = Helper.legalizeInstrStep(*NewMI);
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if (Result == LegalizerHelper::UnableToLegalize) {
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return false;
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}
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return true;
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}
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}
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}
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@ -24,6 +24,9 @@ class ARMSubtarget;
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class ARMLegalizerInfo : public LegalizerInfo {
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public:
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ARMLegalizerInfo(const ARMSubtarget &ST);
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bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const override;
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};
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} // End llvm namespace.
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#endif
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@ -1,7 +1,8 @@
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; RUN: llc -mtriple arm-gnueabi -mattr=+hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV
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; RUN: llc -mtriple arm-gnueabi -mattr=-hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT-AEABI
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; RUN: llc -mtriple arm-gnu -mattr=+hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV
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; RUN: llc -mtriple arm-gnu -mattr=-hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT-DEFAULT
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; We use V6 ops so we can easily check for the extensions (sxth vs bit tricks).
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; RUN: llc -mtriple arm-gnueabi -mattr=+v6,+hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV
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; RUN: llc -mtriple arm-gnueabi -mattr=+v6,-hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT-AEABI
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; RUN: llc -mtriple arm-gnu -mattr=+v6,+hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV
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; RUN: llc -mtriple arm-gnu -mattr=+v6,-hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT-DEFAULT
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define arm_aapcscc i32 @test_sdiv_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: test_sdiv_i32:
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@ -21,3 +22,47 @@ define arm_aapcscc i32 @test_udiv_i32(i32 %a, i32 %b) {
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ret i32 %r
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}
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define arm_aapcscc i16 @test_sdiv_i16(i16 %a, i16 %b) {
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; CHECK-LABEL: test_sdiv_i16:
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; CHECK-DAG: sxth r0, r0
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; CHECK-DAG: sxth r1, r1
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; HWDIV: sdiv r0, r0, r1
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; SOFT-AEABI: blx __aeabi_idiv
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; SOFT-DEFAULT: blx __divsi3
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%r = sdiv i16 %a, %b
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ret i16 %r
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}
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define arm_aapcscc i16 @test_udiv_i16(i16 %a, i16 %b) {
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; CHECK-LABEL: test_udiv_i16:
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; CHECK-DAG: uxth r0, r0
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; CHECK-DAG: uxth r1, r1
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; HWDIV: udiv r0, r0, r1
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; SOFT-AEABI: blx __aeabi_uidiv
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; SOFT-DEFAULT: blx __udivsi3
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%r = udiv i16 %a, %b
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ret i16 %r
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}
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define arm_aapcscc i8 @test_sdiv_i8(i8 %a, i8 %b) {
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; CHECK-LABEL: test_sdiv_i8:
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; CHECK-DAG: sxtb r0, r0
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; CHECK-DAG: sxtb r1, r1
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; HWDIV: sdiv r0, r0, r1
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; SOFT-AEABI: blx __aeabi_idiv
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; SOFT-DEFAULT: blx __divsi3
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%r = sdiv i8 %a, %b
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ret i8 %r
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}
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define arm_aapcscc i8 @test_udiv_i8(i8 %a, i8 %b) {
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; CHECK-LABEL: test_udiv_i8:
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; CHECK-DAG: uxtb r0, r0
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; CHECK-DAG: uxtb r1, r1
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; HWDIV: udiv r0, r0, r1
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; SOFT-AEABI: blx __aeabi_uidiv
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; SOFT-DEFAULT: blx __udivsi3
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%r = udiv i8 %a, %b
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ret i8 %r
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}
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@ -5,6 +5,12 @@
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--- |
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define void @test_sdiv_i32() { ret void }
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define void @test_udiv_i32() { ret void }
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define void @test_sdiv_i16() { ret void }
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define void @test_udiv_i16() { ret void }
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define void @test_sdiv_i8() { ret void }
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define void @test_udiv_i8() { ret void }
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...
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---
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name: test_sdiv_i32
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@ -74,3 +80,151 @@ body: |
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%r0 = COPY %2(s32)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_sdiv_i16
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# CHECK-LABEL: name: test_sdiv_i16
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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; CHECK-DAG: [[X:%[0-9]+]](s16) = COPY %r0
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; CHECK-DAG: [[Y:%[0-9]+]](s16) = COPY %r1
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; CHECK-DAG: [[X32:%[0-9]+]](s32) = G_SEXT [[X]](s16)
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; CHECK-DAG: [[Y32:%[0-9]+]](s32) = G_SEXT [[Y]](s16)
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%0(s16) = COPY %r0
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%1(s16) = COPY %r1
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; HWDIV: [[R32:%[0-9]+]](s32) = G_SDIV [[X32]], [[Y32]]
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; SOFT: ADJCALLSTACKDOWN
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; SOFT-DAG: %r0 = COPY [[X32]]
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; SOFT-DAG: %r1 = COPY [[Y32]]
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; SOFT-AEABI: BLX $__aeabi_idiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-AEABI: [[R32:%[0-9]+]](s32) = COPY %r0
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; SOFT-DEFAULT: BLX $__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
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; SOFT: ADJCALLSTACKUP
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; CHECK: [[R:%[0-9]+]](s16) = G_TRUNC [[R32]]
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%2(s16) = G_SDIV %0, %1
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; CHECK: %r0 = COPY [[R]]
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%r0 = COPY %2(s16)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_udiv_i16
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# CHECK-LABEL: name: test_udiv_i16
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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; CHECK-DAG: [[X:%[0-9]+]](s16) = COPY %r0
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; CHECK-DAG: [[Y:%[0-9]+]](s16) = COPY %r1
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; CHECK-DAG: [[X32:%[0-9]+]](s32) = G_ZEXT [[X]](s16)
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; CHECK-DAG: [[Y32:%[0-9]+]](s32) = G_ZEXT [[Y]](s16)
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%0(s16) = COPY %r0
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%1(s16) = COPY %r1
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; HWDIV: [[R32:%[0-9]+]](s32) = G_UDIV [[X32]], [[Y32]]
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; SOFT: ADJCALLSTACKDOWN
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; SOFT-DAG: %r0 = COPY [[X32]]
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; SOFT-DAG: %r1 = COPY [[Y32]]
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; SOFT-AEABI: BLX $__aeabi_uidiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-AEABI: [[R32:%[0-9]+]](s32) = COPY %r0
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; SOFT-DEFAULT: BLX $__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
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; SOFT: ADJCALLSTACKUP
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; CHECK: [[R:%[0-9]+]](s16) = G_TRUNC [[R32]]
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%2(s16) = G_UDIV %0, %1
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; CHECK: %r0 = COPY [[R]]
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%r0 = COPY %2(s16)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_sdiv_i8
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# CHECK-LABEL: name: test_sdiv_i8
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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; CHECK-DAG: [[X:%[0-9]+]](s8) = COPY %r0
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; CHECK-DAG: [[Y:%[0-9]+]](s8) = COPY %r1
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; CHECK-DAG: [[X32:%[0-9]+]](s32) = G_SEXT [[X]](s8)
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; CHECK-DAG: [[Y32:%[0-9]+]](s32) = G_SEXT [[Y]](s8)
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%0(s8) = COPY %r0
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%1(s8) = COPY %r1
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; HWDIV: [[R32:%[0-9]+]](s32) = G_SDIV [[X32]], [[Y32]]
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; SOFT: ADJCALLSTACKDOWN
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; SOFT-DAG: %r0 = COPY [[X32]]
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; SOFT-DAG: %r1 = COPY [[Y32]]
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; SOFT-AEABI: BLX $__aeabi_idiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-AEABI: [[R32:%[0-9]+]](s32) = COPY %r0
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; SOFT-DEFAULT: BLX $__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
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; SOFT: ADJCALLSTACKUP
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; CHECK: [[R:%[0-9]+]](s8) = G_TRUNC [[R32]]
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%2(s8) = G_SDIV %0, %1
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; CHECK: %r0 = COPY [[R]]
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%r0 = COPY %2(s8)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_udiv_i8
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# CHECK-LABEL: name: test_udiv_i8
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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; CHECK-DAG: [[X:%[0-9]+]](s8) = COPY %r0
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; CHECK-DAG: [[Y:%[0-9]+]](s8) = COPY %r1
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; CHECK-DAG: [[X32:%[0-9]+]](s32) = G_ZEXT [[X]](s8)
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; CHECK-DAG: [[Y32:%[0-9]+]](s32) = G_ZEXT [[Y]](s8)
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%0(s8) = COPY %r0
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%1(s8) = COPY %r1
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; HWDIV: [[R32:%[0-9]+]](s32) = G_UDIV [[X32]], [[Y32]]
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; SOFT: ADJCALLSTACKDOWN
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; SOFT-DAG: %r0 = COPY [[X32]]
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; SOFT-DAG: %r1 = COPY [[Y32]]
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; SOFT-AEABI: BLX $__aeabi_uidiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-AEABI: [[R32:%[0-9]+]](s32) = COPY %r0
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; SOFT-DEFAULT: BLX $__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
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; SOFT: ADJCALLSTACKUP
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; CHECK: [[R:%[0-9]+]](s8) = G_TRUNC [[R32]]
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%2(s8) = G_UDIV %0, %1
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; CHECK: %r0 = COPY [[R]]
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%r0 = COPY %2(s8)
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BX_RET 14, _, implicit %r0
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...
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