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AArch64: estimate inline asm length during branch relaxation

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To make sure branches are in range, we need to do a better job of estimating
the length of an inline assembly block than "it's probably 1 instruction, who'd
write asm with more than that?".

Fortunately there's already a (highly suspect, see how many ways you can think
of to break it!) callback for this purpose, which is used by the other targets.

rdar://problem/17277590

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211095 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2014-06-17 11:31:42 +00:00
parent 3a001aab4d
commit c22960dba6
2 changed files with 42 additions and 1 deletions
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8
lib/Target/AArch64/AArch64InstrInfo.cpp
View File

@ -35,8 +35,14 @@ AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI)
/// GetInstSize - Return the number of bytes of code the specified /// GetInstSize - Return the number of bytes of code the specified
/// instruction may be. This returns the maximum number of bytes. /// instruction may be. This returns the maximum number of bytes.
unsigned AArch64InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { unsigned AArch64InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
const MCInstrDesc &Desc = MI->getDesc(); const MachineBasicBlock &MBB = *MI->getParent();
const MachineFunction *MF = MBB.getParent();
const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
if (MI->getOpcode() == AArch64::INLINEASM)
return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
const MCInstrDesc &Desc = MI->getDesc();
switch (Desc.getOpcode()) { switch (Desc.getOpcode()) {
default: default:
// Anything not explicitly designated otherwise is a nomal 4-byte insn. // Anything not explicitly designated otherwise is a nomal 4-byte insn.

35
test/CodeGen/AArch64/branch-relax-asm.ll Normal file
View File

@ -0,0 +1,35 @@
; RUN: llc -mtriple=aarch64-apple-ios7.0 -disable-block-placement -aarch64-tbz-offset-bits=4 -o - %s | FileCheck %s
define i32 @test_asm_length(i32 %in) {
; CHECK-LABEL: test_asm_length:
; It would be more natural to use just one "tbnz %false" here, but if the
; number of instructions in the asm is counted reasonably, that block is out
; of the limited range we gave tbz. So branch relaxation has to invert the
; condition.
; CHECK: tbz w0, #0, [[TRUE:LBB[0-9]+_[0-9]+]]
; CHECK: b [[FALSE:LBB[0-9]+_[0-9]+]]
; CHECK: [[TRUE]]:
; CHECK: orr w0, wzr, #0x4
; CHECK: nop
; CHECK: nop
; CHECK: nop
; CHECK: nop
; CHECK: nop
; CHECK: nop
; CHECK: ret
; CHECK: [[FALSE]]:
; CHECK: ret
%val = and i32 %in, 1
%tst = icmp eq i32 %val, 0
br i1 %tst, label %true, label %false
true:
call void asm sideeffect "nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop", ""()
ret i32 4
false:
ret i32 0
}