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llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.

Browse Source 
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Torok Edwin 2009-07-14 16:55:14 +00:00
parent 1f316e321a
commit c23197a26f
172 changed files with 813 additions and 812 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
include/llvm/Analysis/ScalarEvolutionExpressions.h
View File

@ -584,12 +584,12 @@ namespace llvm {
case scCouldNotCompute:
return ((SC*)this)->visitCouldNotCompute((const SCEVCouldNotCompute*)S);
default:
LLVM_UNREACHABLE("Unknown SCEV type!");
llvm_unreachable("Unknown SCEV type!");
}
}
RetVal visitCouldNotCompute(const SCEVCouldNotCompute *S) {
LLVM_UNREACHABLE("Invalid use of SCEVCouldNotCompute!");
llvm_unreachable("Invalid use of SCEVCouldNotCompute!");
return RetVal();
}
};

2
include/llvm/MDNode.h
View File

@ -120,7 +120,7 @@ public:
virtual void destroyConstant();
virtual void replaceUsesOfWithOnConstant(Value *From, Value *To, Use *U) {
LLVM_UNREACHABLE("This should never be called because MDNodes have no ops");
llvm_unreachable("This should never be called because MDNodes have no ops");
}
/// Methods for support type inquiry through isa, cast, and dyn_cast:

19
include/llvm/Support/ErrorHandling.h
View File

@ -47,19 +47,20 @@ namespace llvm {
void llvm_report_error(const std::string &reason) NORETURN;
/// This function calls abort(), and prints the optional message to stderr.
/// Call this instead of assert(0), so that compiler knows the path is not
/// reachable even for NDEBUG builds.
/// Use the LLVM_UNREACHABLE macro instead that adds location info.
void llvm_unreachable(const char *msg=0, const char *file=0,
unsigned line=0) NORETURN;
/// Use the llvm_unreachable macro (that adds location info), instead of
/// calling this function directly.
void llvm_unreachable_internal(const char *msg=0, const char *file=0,
unsigned line=0) NORETURN;
}
/// Macro that calls llvm_unreachable with location info and message in
/// debug mode. In NDEBUG mode it calls llvm_unreachable with no message.
/// Prints the message and location info to stderr in !NDEBUG builds.
/// In NDEBUG mode it only prints "UNREACHABLE executed".
/// Use this instead of assert(0), so that the compiler knows this path
/// is not reachable even for NDEBUG builds.
#ifndef NDEBUG
#define LLVM_UNREACHABLE(msg) llvm_unreachable(msg, __FILE__, __LINE__)
#define llvm_unreachable(msg) llvm_unreachable_internal(msg, __FILE__, __LINE__)
#else
#define LLVM_UNREACHABLE(msg) llvm_unreachable()
#define llvm_unreachable(msg) llvm_unreachable_internal()
#endif
#endif

2
include/llvm/Support/InstVisitor.h
View File

@ -114,7 +114,7 @@ public:
//
RetTy visit(Instruction &I) {
switch (I.getOpcode()) {
default: LLVM_UNREACHABLE("Unknown instruction type encountered!");
default: llvm_unreachable("Unknown instruction type encountered!");
// Build the switch statement using the Instruction.def file...
#define HANDLE_INST(NUM, OPCODE, CLASS) \
case Instruction::OPCODE: return \

2
include/llvm/Support/PassNameParser.h
View File

@ -68,7 +68,7 @@ public:
if (findOption(P->getPassArgument()) != getNumOptions()) {
cerr << "Two passes with the same argument (-"
<< P->getPassArgument() << ") attempted to be registered!\n";
LLVM_UNREACHABLE(0);
llvm_unreachable(0);
}
addLiteralOption(P->getPassArgument(), P, P->getPassName());
}

2
include/llvm/Target/TargetInstrInfo.h
View File

@ -429,7 +429,7 @@ public:
/// point.
virtual void insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const {
LLVM_UNREACHABLE("Target didn't implement insertNoop!");
llvm_unreachable("Target didn't implement insertNoop!");
}
/// isPredicated - Returns true if the instruction is already predicated.

4
lib/Analysis/AliasAnalysisCounter.cpp
View File

@ -132,7 +132,7 @@ AliasAnalysisCounter::alias(const Value *V1, unsigned V1Size,
const char *AliasString;
switch (R) {
default: LLVM_UNREACHABLE("Unknown alias type!");
default: llvm_unreachable("Unknown alias type!");
case NoAlias: No++; AliasString = "No alias"; break;
case MayAlias: May++; AliasString = "May alias"; break;
case MustAlias: Must++; AliasString = "Must alias"; break;
@ -157,7 +157,7 @@ AliasAnalysisCounter::getModRefInfo(CallSite CS, Value *P, unsigned Size) {
const char *MRString;
switch (R) {
default: LLVM_UNREACHABLE("Unknown mod/ref type!");
default: llvm_unreachable("Unknown mod/ref type!");
case NoModRef: NoMR++; MRString = "NoModRef"; break;
case Ref: JustRef++; MRString = "JustRef"; break;
case Mod: JustMod++; MRString = "JustMod"; break;

2
lib/Analysis/AliasSetTracker.cpp
View File

@ -540,7 +540,7 @@ void AliasSet::print(std::ostream &OS) const {
case Refs : OS << "Ref "; break;
case Mods : OS << "Mod "; break;
case ModRef : OS << "Mod/Ref "; break;
default: LLVM_UNREACHABLE("Bad value for AccessTy!");
default: llvm_unreachable("Bad value for AccessTy!");
}
if (isVolatile()) OS << "[volatile] ";
if (Forward)

2
lib/Analysis/BasicAliasAnalysis.cpp
View File

@ -158,7 +158,7 @@ namespace {
virtual void getArgumentAccesses(Function *F, CallSite CS,
std::vector<PointerAccessInfo> &Info) {
LLVM_UNREACHABLE("This method may not be called on this function!");
llvm_unreachable("This method may not be called on this function!");
}
virtual void getMustAliases(Value *P, std::vector<Value*> &RetVals) { }

6
lib/Analysis/ConstantFolding.cpp
View File

@ -366,7 +366,7 @@ Constant *llvm::ConstantFoldInstOperands(unsigned Opcode, const Type *DestTy,
return 0;
case Instruction::ICmp:
case Instruction::FCmp:
LLVM_UNREACHABLE("This function is invalid for compares: no predicate specified");
llvm_unreachable("This function is invalid for compares: no predicate specified");
case Instruction::PtrToInt:
// If the input is a inttoptr, eliminate the pair. This requires knowing
// the width of a pointer, so it can't be done in ConstantExpr::getCast.
@ -691,7 +691,7 @@ static Constant *ConstantFoldFP(double (*NativeFP)(double), double V,
return Context->getConstantFP(APFloat((float)V));
if (Ty == Type::DoubleTy)
return Context->getConstantFP(APFloat(V));
LLVM_UNREACHABLE("Can only constant fold float/double");
llvm_unreachable("Can only constant fold float/double");
return 0; // dummy return to suppress warning
}
@ -710,7 +710,7 @@ static Constant *ConstantFoldBinaryFP(double (*NativeFP)(double, double),
return Context->getConstantFP(APFloat((float)V));
if (Ty == Type::DoubleTy)
return Context->getConstantFP(APFloat(V));
LLVM_UNREACHABLE("Can only constant fold float/double");
llvm_unreachable("Can only constant fold float/double");
return 0; // dummy return to suppress warning
}

14
lib/Analysis/IPA/Andersens.cpp
View File

@ -508,7 +508,7 @@ namespace {
#ifndef NDEBUG
V->dump();
#endif
LLVM_UNREACHABLE("Value does not have a node in the points-to graph!");
llvm_unreachable("Value does not have a node in the points-to graph!");
}
return I->second;
}
@ -827,10 +827,10 @@ unsigned Andersens::getNodeForConstantPointer(Constant *C) {
return getNodeForConstantPointer(CE->getOperand(0));
default:
cerr << "Constant Expr not yet handled: " << *CE << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
} else {
LLVM_UNREACHABLE("Unknown constant pointer!");
llvm_unreachable("Unknown constant pointer!");
}
return 0;
}
@ -854,10 +854,10 @@ unsigned Andersens::getNodeForConstantPointerTarget(Constant *C) {
return getNodeForConstantPointerTarget(CE->getOperand(0));
default:
cerr << "Constant Expr not yet handled: " << *CE << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
} else {
LLVM_UNREACHABLE("Unknown constant pointer!");
llvm_unreachable("Unknown constant pointer!");
}
return 0;
}
@ -1154,7 +1154,7 @@ void Andersens::visitInstruction(Instruction &I) {
default:
// Is this something we aren't handling yet?
cerr << "Unknown instruction: " << I;
llvm_unreachable();
llvm_unreachable(0);
}
}
@ -1244,7 +1244,7 @@ void Andersens::visitSelectInst(SelectInst &SI) {
}
void Andersens::visitVAArg(VAArgInst &I) {
LLVM_UNREACHABLE("vaarg not handled yet!");
llvm_unreachable("vaarg not handled yet!");
}
/// AddConstraintsForCall - Add constraints for a call with actual arguments

2
lib/Analysis/InstCount.cpp
View File

@ -48,7 +48,7 @@ namespace {
void visitInstruction(Instruction &I) {
cerr << "Instruction Count does not know about " << I;
llvm_unreachable();
llvm_unreachable(0);
}
public:
static char ID; // Pass identification, replacement for typeid

2
lib/Analysis/LoopDependenceAnalysis.cpp
View File

@ -64,7 +64,7 @@ static Value *GetPointerOperand(Value *I) {
return i->getPointerOperand();
if (StoreInst *i = dyn_cast<StoreInst>(I))
return i->getPointerOperand();
LLVM_UNREACHABLE("Value is no load or store instruction!");
llvm_unreachable("Value is no load or store instruction!");
// Never reached.
return 0;
}

16
lib/Analysis/ScalarEvolution.cpp
View File

@ -148,17 +148,17 @@ SCEVCouldNotCompute::SCEVCouldNotCompute() :
SCEV(FoldingSetNodeID(), scCouldNotCompute) {}
bool SCEVCouldNotCompute::isLoopInvariant(const Loop *L) const {
LLVM_UNREACHABLE("Attempt to use a SCEVCouldNotCompute object!");
llvm_unreachable("Attempt to use a SCEVCouldNotCompute object!");
return false;
}
const Type *SCEVCouldNotCompute::getType() const {
LLVM_UNREACHABLE("Attempt to use a SCEVCouldNotCompute object!");
llvm_unreachable("Attempt to use a SCEVCouldNotCompute object!");
return 0;
}
bool SCEVCouldNotCompute::hasComputableLoopEvolution(const Loop *L) const {
LLVM_UNREACHABLE("Attempt to use a SCEVCouldNotCompute object!");
llvm_unreachable("Attempt to use a SCEVCouldNotCompute object!");
return false;
}
@ -285,7 +285,7 @@ SCEVCommutativeExpr::replaceSymbolicValuesWithConcrete(
else if (isa<SCEVUMaxExpr>(this))
return SE.getUMaxExpr(NewOps);
else
LLVM_UNREACHABLE("Unknown commutative expr!");
llvm_unreachable("Unknown commutative expr!");
}
}
return this;
@ -506,7 +506,7 @@ namespace {
return operator()(LC->getOperand(), RC->getOperand());
}
LLVM_UNREACHABLE("Unknown SCEV kind!");
llvm_unreachable("Unknown SCEV kind!");
return false;
}
};
@ -3475,7 +3475,7 @@ GetAddressedElementFromGlobal(LLVMContext *Context, GlobalVariable *GV,
if (Idx >= ATy->getNumElements()) return 0; // Bogus program
Init = Context->getNullValue(ATy->getElementType());
} else {
LLVM_UNREACHABLE("Unknown constant aggregate type!");
llvm_unreachable("Unknown constant aggregate type!");
}
return 0;
} else {
@ -3885,7 +3885,7 @@ const SCEV *ScalarEvolution::getSCEVAtScope(const SCEV *V, const Loop *L) {
return getSMaxExpr(NewOps);
if (isa<SCEVUMaxExpr>(Comm))
return getUMaxExpr(NewOps);
LLVM_UNREACHABLE("Unknown commutative SCEV type!");
llvm_unreachable("Unknown commutative SCEV type!");
}
}
// If we got here, all operands are loop invariant.
@ -3936,7 +3936,7 @@ const SCEV *ScalarEvolution::getSCEVAtScope(const SCEV *V, const Loop *L) {
return getTruncateExpr(Op, Cast->getType());
}
LLVM_UNREACHABLE("Unknown SCEV type!");
llvm_unreachable("Unknown SCEV type!");
return 0;
}

2
lib/AsmParser/LLLexer.cpp
View File

@ -700,7 +700,7 @@ lltok::Kind LLLexer::Lex0x() {
uint64_t Pair[2];
switch (Kind) {
default: LLVM_UNREACHABLE("Unknown kind!");
default: llvm_unreachable("Unknown kind!");
case 'K':
// F80HexFPConstant - x87 long double in hexadecimal format (10 bytes)
FP80HexToIntPair(TokStart+3, CurPtr, Pair);

4
lib/AsmParser/LLParser.cpp
View File

@ -2041,7 +2041,7 @@ bool LLParser::ConvertGlobalValIDToValue(const Type *Ty, ValID &ID,
return Error(ID.Loc, "functions are not values, refer to them as pointers");
switch (ID.Kind) {
default: LLVM_UNREACHABLE("Unknown ValID!");
default: llvm_unreachable("Unknown ValID!");
case ValID::t_LocalID:
case ValID::t_LocalName:
return Error(ID.Loc, "invalid use of function-local name");
@ -2836,7 +2836,7 @@ bool LLParser::ParseArithmetic(Instruction *&Inst, PerFunctionState &PFS,
bool Valid;
switch (OperandType) {
default: LLVM_UNREACHABLE("Unknown operand type!");
default: llvm_unreachable("Unknown operand type!");
case 0: // int or FP.
Valid = LHS->getType()->isIntOrIntVector() ||
LHS->getType()->isFPOrFPVector();

40
lib/Bitcode/Writer/BitcodeWriter.cpp
View File

@ -59,7 +59,7 @@ enum {
static unsigned GetEncodedCastOpcode(unsigned Opcode) {
switch (Opcode) {
default: LLVM_UNREACHABLE("Unknown cast instruction!");
default: llvm_unreachable("Unknown cast instruction!");
case Instruction::Trunc : return bitc::CAST_TRUNC;
case Instruction::ZExt : return bitc::CAST_ZEXT;
case Instruction::SExt : return bitc::CAST_SEXT;
@ -77,7 +77,7 @@ static unsigned GetEncodedCastOpcode(unsigned Opcode) {
static unsigned GetEncodedBinaryOpcode(unsigned Opcode) {
switch (Opcode) {
default: LLVM_UNREACHABLE("Unknown binary instruction!");
default: llvm_unreachable("Unknown binary instruction!");
case Instruction::Add:
case Instruction::FAdd: return bitc::BINOP_ADD;
case Instruction::Sub:
@ -201,7 +201,7 @@ static void WriteTypeTable(const ValueEnumerator &VE, BitstreamWriter &Stream) {
unsigned Code = 0;
switch (T->getTypeID()) {
default: LLVM_UNREACHABLE("Unknown type!");
default: llvm_unreachable("Unknown type!");
case Type::VoidTyID: Code = bitc::TYPE_CODE_VOID; break;
case Type::FloatTyID: Code = bitc::TYPE_CODE_FLOAT; break;
case Type::DoubleTyID: Code = bitc::TYPE_CODE_DOUBLE; break;
@ -279,7 +279,7 @@ static void WriteTypeTable(const ValueEnumerator &VE, BitstreamWriter &Stream) {
static unsigned getEncodedLinkage(const GlobalValue *GV) {
switch (GV->getLinkage()) {
default: LLVM_UNREACHABLE("Invalid linkage!");
default: llvm_unreachable("Invalid linkage!");
case GlobalValue::GhostLinkage: // Map ghost linkage onto external.
case GlobalValue::ExternalLinkage: return 0;
case GlobalValue::WeakAnyLinkage: return 1;
@ -299,7 +299,7 @@ static unsigned getEncodedLinkage(const GlobalValue *GV) {
static unsigned getEncodedVisibility(const GlobalValue *GV) {
switch (GV->getVisibility()) {
default: LLVM_UNREACHABLE("Invalid visibility!");
default: llvm_unreachable("Invalid visibility!");
case GlobalValue::DefaultVisibility: return 0;
case GlobalValue::HiddenVisibility: return 1;
case GlobalValue::ProtectedVisibility: return 2;
@ -713,7 +713,7 @@ static void WriteConstants(unsigned FirstVal, unsigned LastVal,
}
}
} else {
LLVM_UNREACHABLE("Unknown constant!");
llvm_unreachable("Unknown constant!");
}
Stream.EmitRecord(Code, Record, AbbrevToUse);
Record.clear();
@ -1127,7 +1127,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 8));
if (Stream.EmitBlockInfoAbbrev(bitc::VALUE_SYMTAB_BLOCK_ID,
Abbv) != VST_ENTRY_8_ABBREV)
LLVM_UNREACHABLE("Unexpected abbrev ordering!");
llvm_unreachable("Unexpected abbrev ordering!");
}
{ // 7-bit fixed width VST_ENTRY strings.
@ -1138,7 +1138,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 7));
if (Stream.EmitBlockInfoAbbrev(bitc::VALUE_SYMTAB_BLOCK_ID,
Abbv) != VST_ENTRY_7_ABBREV)
LLVM_UNREACHABLE("Unexpected abbrev ordering!");
llvm_unreachable("Unexpected abbrev ordering!");
}
{ // 6-bit char6 VST_ENTRY strings.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
@ -1148,7 +1148,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Char6));
if (Stream.EmitBlockInfoAbbrev(bitc::VALUE_SYMTAB_BLOCK_ID,
Abbv) != VST_ENTRY_6_ABBREV)
LLVM_UNREACHABLE("Unexpected abbrev ordering!");
llvm_unreachable("Unexpected abbrev ordering!");
}
{ // 6-bit char6 VST_BBENTRY strings.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
@ -1158,7 +1158,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Char6));
if (Stream.EmitBlockInfoAbbrev(bitc::VALUE_SYMTAB_BLOCK_ID,
Abbv) != VST_BBENTRY_6_ABBREV)
LLVM_UNREACHABLE("Unexpected abbrev ordering!");
llvm_unreachable("Unexpected abbrev ordering!");
}
@ -1170,7 +1170,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Log2_32_Ceil(VE.getTypes().size()+1)));
if (Stream.EmitBlockInfoAbbrev(bitc::CONSTANTS_BLOCK_ID,
Abbv) != CONSTANTS_SETTYPE_ABBREV)
LLVM_UNREACHABLE("Unexpected abbrev ordering!");
llvm_unreachable("Unexpected abbrev ordering!");
}
{ // INTEGER abbrev for CONSTANTS_BLOCK.
@ -1179,7 +1179,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 8));
if (Stream.EmitBlockInfoAbbrev(bitc::CONSTANTS_BLOCK_ID,
Abbv) != CONSTANTS_INTEGER_ABBREV)
LLVM_UNREACHABLE("Unexpected abbrev ordering!");
llvm_unreachable("Unexpected abbrev ordering!");
}
{ // CE_CAST abbrev for CONSTANTS_BLOCK.
@ -1192,14 +1192,14 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
if (Stream.EmitBlockInfoAbbrev(bitc::CONSTANTS_BLOCK_ID,
Abbv) != CONSTANTS_CE_CAST_Abbrev)
LLVM_UNREACHABLE("Unexpected abbrev ordering!");
llvm_unreachable("Unexpected abbrev ordering!");
}
{ // NULL abbrev for CONSTANTS_BLOCK.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::CST_CODE_NULL));
if (Stream.EmitBlockInfoAbbrev(bitc::CONSTANTS_BLOCK_ID,
Abbv) != CONSTANTS_NULL_Abbrev)
LLVM_UNREACHABLE("Unexpected abbrev ordering!");
llvm_unreachable("Unexpected abbrev ordering!");
}
// FIXME: This should only use space for first class types!
@ -1212,7 +1212,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 1)); // volatile
if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID,
Abbv) != FUNCTION_INST_LOAD_ABBREV)
LLVM_UNREACHABLE("Unexpected abbrev ordering!");
llvm_unreachable("Unexpected abbrev ordering!");
}
{ // INST_BINOP abbrev for FUNCTION_BLOCK.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
@ -1222,7 +1222,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 4)); // opc
if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID,
Abbv) != FUNCTION_INST_BINOP_ABBREV)
LLVM_UNREACHABLE("Unexpected abbrev ordering!");
llvm_unreachable("Unexpected abbrev ordering!");
}
{ // INST_CAST abbrev for FUNCTION_BLOCK.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
@ -1233,7 +1233,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 4)); // opc
if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID,
Abbv) != FUNCTION_INST_CAST_ABBREV)
LLVM_UNREACHABLE("Unexpected abbrev ordering!");
llvm_unreachable("Unexpected abbrev ordering!");
}
{ // INST_RET abbrev for FUNCTION_BLOCK.
@ -1241,7 +1241,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv->Add(BitCodeAbbrevOp(bitc::FUNC_CODE_INST_RET));
if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID,
Abbv) != FUNCTION_INST_RET_VOID_ABBREV)
LLVM_UNREACHABLE("Unexpected abbrev ordering!");
llvm_unreachable("Unexpected abbrev ordering!");
}
{ // INST_RET abbrev for FUNCTION_BLOCK.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
@ -1249,14 +1249,14 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // ValID
if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID,
Abbv) != FUNCTION_INST_RET_VAL_ABBREV)
LLVM_UNREACHABLE("Unexpected abbrev ordering!");
llvm_unreachable("Unexpected abbrev ordering!");
}
{ // INST_UNREACHABLE abbrev for FUNCTION_BLOCK.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::FUNC_CODE_INST_UNREACHABLE));
if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID,
Abbv) != FUNCTION_INST_UNREACHABLE_ABBREV)
LLVM_UNREACHABLE("Unexpected abbrev ordering!");
llvm_unreachable("Unexpected abbrev ordering!");
}
Stream.ExitBlock();

16
lib/CodeGen/AsmPrinter/AsmPrinter.cpp
View File

@ -238,7 +238,7 @@ bool AsmPrinter::doFinalization(Module &M) {
else if (I->hasWeakLinkage())
O << TAI->getWeakRefDirective() << Name << '\n';
else if (!I->hasLocalLinkage())
LLVM_UNREACHABLE("Invalid alias linkage");
llvm_unreachable("Invalid alias linkage");
printVisibility(Name, I->getVisibility());
@ -902,7 +902,7 @@ void AsmPrinter::EmitConstantValueOnly(const Constant *CV) {
case Instruction::SIToFP:
case Instruction::FPToUI:
case Instruction::FPToSI:
LLVM_UNREACHABLE("FIXME: Don't yet support this kind of constant cast expr");
llvm_unreachable("FIXME: Don't yet support this kind of constant cast expr");
break;
case Instruction::BitCast:
return EmitConstantValueOnly(CE->getOperand(0));
@ -968,10 +968,10 @@ void AsmPrinter::EmitConstantValueOnly(const Constant *CV) {
O << ')';
break;
default:
LLVM_UNREACHABLE("Unsupported operator!");
llvm_unreachable("Unsupported operator!");
}
} else {
LLVM_UNREACHABLE("Unknown constant value!");
llvm_unreachable("Unknown constant value!");
}
}
@ -1210,7 +1210,7 @@ void AsmPrinter::EmitGlobalConstantFP(const ConstantFP *CFP,
O << '\n';
}
return;
} else LLVM_UNREACHABLE("Floating point constant type not handled");
} else llvm_unreachable("Floating point constant type not handled");
}
void AsmPrinter::EmitGlobalConstantLargeInt(const ConstantInt *CI,
@ -1302,7 +1302,7 @@ void AsmPrinter::EmitGlobalConstant(const Constant *CV, unsigned AddrSpace) {
void AsmPrinter::EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
// Target doesn't support this yet!
LLVM_UNREACHABLE("Target does not support EmitMachineConstantPoolValue");
llvm_unreachable("Target does not support EmitMachineConstantPoolValue");
}
/// PrintSpecial - Print information related to the specified machine instr
@ -1661,7 +1661,7 @@ void AsmPrinter::printDataDirective(const Type *type, unsigned AddrSpace) {
"Target cannot handle 64-bit constant exprs!");
O << TAI->getData64bitsDirective(AddrSpace);
} else {
LLVM_UNREACHABLE("Target cannot handle given data directive width!");
llvm_unreachable("Target cannot handle given data directive width!");
}
break;
}
@ -1747,7 +1747,7 @@ GCMetadataPrinter *AsmPrinter::GetOrCreateGCPrinter(GCStrategy *S) {
}
cerr << "no GCMetadataPrinter registered for GC: " << Name << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
/// EmitComments - Pretty-print comments for instructions

8
lib/CodeGen/AsmPrinter/DIE.cpp
View File

@ -207,7 +207,7 @@ void DIEInteger::EmitValue(Dwarf *D, unsigned Form) const {
case dwarf::DW_FORM_data8: Asm->EmitInt64(Integer); break;
case dwarf::DW_FORM_udata: Asm->EmitULEB128Bytes(Integer); break;
case dwarf::DW_FORM_sdata: Asm->EmitSLEB128Bytes(Integer); break;
default: LLVM_UNREACHABLE("DIE Value form not supported yet");
default: llvm_unreachable("DIE Value form not supported yet");
}
}
@ -226,7 +226,7 @@ unsigned DIEInteger::SizeOf(const TargetData *TD, unsigned Form) const {
case dwarf::DW_FORM_data8: return sizeof(int64_t);
case dwarf::DW_FORM_udata: return TargetAsmInfo::getULEB128Size(Integer);
case dwarf::DW_FORM_sdata: return TargetAsmInfo::getSLEB128Size(Integer);
default: LLVM_UNREACHABLE("DIE Value form not supported yet"); break;
default: llvm_unreachable("DIE Value form not supported yet"); break;
}
return 0;
}
@ -482,7 +482,7 @@ void DIEBlock::EmitValue(Dwarf *D, unsigned Form) const {
case dwarf::DW_FORM_block2: Asm->EmitInt16(Size); break;
case dwarf::DW_FORM_block4: Asm->EmitInt32(Size); break;
case dwarf::DW_FORM_block: Asm->EmitULEB128Bytes(Size); break;
default: LLVM_UNREACHABLE("Improper form for block"); break;
default: llvm_unreachable("Improper form for block"); break;
}
const SmallVector<DIEAbbrevData, 8> &AbbrevData = Abbrev.getData();
@ -500,7 +500,7 @@ unsigned DIEBlock::SizeOf(const TargetData *TD, unsigned Form) const {
case dwarf::DW_FORM_block2: return Size + sizeof(int16_t);
case dwarf::DW_FORM_block4: return Size + sizeof(int32_t);
case dwarf::DW_FORM_block: return Size + TargetAsmInfo::getULEB128Size(Size);
default: LLVM_UNREACHABLE("Improper form for block"); break;
default: llvm_unreachable("Improper form for block"); break;
}
return 0;
}

4
lib/CodeGen/AsmPrinter/DwarfPrinter.cpp
View File

@ -191,7 +191,7 @@ void Dwarf::EmitFrameMoves(const char *BaseLabel, unsigned BaseLabelID,
Asm->EmitULEB128Bytes(Offset);
Asm->EOL("Offset");
} else {
LLVM_UNREACHABLE("Machine move not supported yet.");
llvm_unreachable("Machine move not supported yet.");
}
} else if (Src.isReg() &&
Src.getReg() == MachineLocation::VirtualFP) {
@ -201,7 +201,7 @@ void Dwarf::EmitFrameMoves(const char *BaseLabel, unsigned BaseLabelID,
Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Dst.getReg(), isEH));
Asm->EOL("Register");
} else {
LLVM_UNREACHABLE("Machine move not supported yet.");
llvm_unreachable("Machine move not supported yet.");
}
} else {
unsigned Reg = RI->getDwarfRegNum(Src.getReg(), isEH);

2
lib/CodeGen/BranchFolding.cpp
View File

@ -462,7 +462,7 @@ static bool MergeCompare(const std::pair<unsigned,MachineBasicBlock*> &p,
// _GLIBCXX_DEBUG checks strict weak ordering, which involves comparing
// an object with itself.
#ifndef _GLIBCXX_DEBUG
LLVM_UNREACHABLE("Predecessor appears twice");
llvm_unreachable("Predecessor appears twice");
#endif
return false;
}

2
lib/CodeGen/ELFCodeEmitter.cpp
View File

@ -108,7 +108,7 @@ bool ELFCodeEmitter::finishFunction(MachineFunction &MF) {
MR.setResultPointer((void*)Addr);
MR.setConstantVal(JumpTableSectionIdx);
} else {
LLVM_UNREACHABLE("Unhandled relocation type");
llvm_unreachable("Unhandled relocation type");
}
ES->addRelocation(MR);
}

10
lib/CodeGen/ELFWriter.cpp
View File

@ -149,7 +149,7 @@ bool ELFWriter::doInitialization(Module &M) {
unsigned ELFWriter::getGlobalELFVisibility(const GlobalValue *GV) {
switch (GV->getVisibility()) {
default:
LLVM_UNREACHABLE("unknown visibility type");
llvm_unreachable("unknown visibility type");
case GlobalValue::DefaultVisibility:
return ELFSym::STV_DEFAULT;
case GlobalValue::HiddenVisibility:
@ -359,9 +359,9 @@ void ELFWriter::EmitGlobalConstant(const Constant *CV, ELFSection &GblS) {
else if (CFP->getType() == Type::FloatTy)
GblS.emitWord32(Val);
else if (CFP->getType() == Type::X86_FP80Ty) {
LLVM_UNREACHABLE("X86_FP80Ty global emission not implemented");
llvm_unreachable("X86_FP80Ty global emission not implemented");
} else if (CFP->getType() == Type::PPC_FP128Ty)
LLVM_UNREACHABLE("PPC_FP128Ty global emission not implemented");
llvm_unreachable("PPC_FP128Ty global emission not implemented");
return;
} else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
if (Size == 4)
@ -369,7 +369,7 @@ void ELFWriter::EmitGlobalConstant(const Constant *CV, ELFSection &GblS) {
else if (Size == 8)
GblS.emitWord64(CI->getZExtValue());
else
LLVM_UNREACHABLE("LargeInt global emission not implemented");
llvm_unreachable("LargeInt global emission not implemented");
return;
} else if (const ConstantVector *CP = dyn_cast<ConstantVector>(CV)) {
const VectorType *PTy = CP->getType();
@ -377,7 +377,7 @@ void ELFWriter::EmitGlobalConstant(const Constant *CV, ELFSection &GblS) {
EmitGlobalConstant(CP->getOperand(I), GblS);
return;
}
LLVM_UNREACHABLE("unknown global constant");
llvm_unreachable("unknown global constant");
}

4
lib/CodeGen/GCMetadata.cpp
View File

@ -95,7 +95,7 @@ GCStrategy *GCModuleInfo::getOrCreateStrategy(const Module *M,
}
cerr << "unsupported GC: " << Name << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
GCFunctionInfo &GCModuleInfo::getFunctionInfo(const Function &F) {
@ -144,7 +144,7 @@ void Printer::getAnalysisUsage(AnalysisUsage &AU) const {
static const char *DescKind(GC::PointKind Kind) {
switch (Kind) {
default: LLVM_UNREACHABLE("Unknown GC point kind");
default: llvm_unreachable("Unknown GC point kind");
case GC::Loop: return "loop";
case GC::Return: return "return";
case GC::PreCall: return "pre-call";

2
lib/CodeGen/GCStrategy.cpp
View File

@ -109,7 +109,7 @@ bool GCStrategy::initializeCustomLowering(Module &M) { return false; }
bool GCStrategy::performCustomLowering(Function &F) {
cerr << "gc " << getName() << " must override performCustomLowering.\n";
llvm_unreachable();
llvm_unreachable(0);
return 0;
}

4
lib/CodeGen/IfConversion.cpp
View File

@ -1135,7 +1135,7 @@ void IfConverter::PredicateBlock(BBInfo &BBI,
#ifndef NDEBUG
cerr << "Unable to predicate " << *I << "!\n";
#endif
llvm_unreachable();
llvm_unreachable(0);
}
}
@ -1171,7 +1171,7 @@ void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
#ifndef NDEBUG
cerr << "Unable to predicate " << *I << "!\n";
#endif
llvm_unreachable();
llvm_unreachable(0);
}
}

4
lib/CodeGen/IntrinsicLowering.cpp
View File

@ -157,7 +157,7 @@ static Value *LowerBSWAP(Value *V, Instruction *IP) {
IRBuilder<> Builder(IP->getParent(), IP);
switch(BitSize) {
default: LLVM_UNREACHABLE("Unhandled type size of value to byteswap!");
default: llvm_unreachable("Unhandled type size of value to byteswap!");
case 16: {
Value *Tmp1 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 8),
"bswap.2");
@ -295,7 +295,7 @@ static void ReplaceFPIntrinsicWithCall(CallInst *CI, const char *Fname,
const char *Dname,
const char *LDname) {
switch (CI->getOperand(1)->getType()->getTypeID()) {
default: LLVM_UNREACHABLE("Invalid type in intrinsic");
default: llvm_unreachable("Invalid type in intrinsic");
case Type::FloatTyID:
ReplaceCallWith(Fname, CI, CI->op_begin() + 1, CI->op_end(),
Type::FloatTy);

2
lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -1102,7 +1102,7 @@ unsigned LiveIntervals::getVNInfoSourceReg(const VNInfo *VNI) const {
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
if (tii_->isMoveInstr(*VNI->copy, SrcReg, DstReg, SrcSubReg, DstSubReg))
return SrcReg;
LLVM_UNREACHABLE("Unrecognized copy instruction!");
llvm_unreachable("Unrecognized copy instruction!");
return 0;
}

2
lib/CodeGen/MachOCodeEmitter.cpp
View File

@ -105,7 +105,7 @@ bool MachOCodeEmitter::finishFunction(MachineFunction &MF) {
// FIXME: This should be a set or something that uniques
MOW.PendingGlobals.push_back(MR.getGlobalValue());
} else {
LLVM_UNREACHABLE("Unhandled relocation type");
llvm_unreachable("Unhandled relocation type");
}
MOS->addRelocation(MR);
}

10
lib/CodeGen/MachOWriter.cpp
View File

@ -635,7 +635,7 @@ void MachOWriter::InitMem(const Constant *C, uintptr_t Offset,
case Instruction::Add:
default:
cerr << "ConstantExpr not handled as global var init: " << *CE << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
} else if (PC->getType()->isSingleValueType()) {
unsigned char *ptr = (unsigned char *)PA;
@ -669,7 +669,7 @@ void MachOWriter::InitMem(const Constant *C, uintptr_t Offset,
ptr[6] = val >> 48;
ptr[7] = val >> 56;
} else {
LLVM_UNREACHABLE("Not implemented: bit widths > 64");
llvm_unreachable("Not implemented: bit widths > 64");
}
break;
}
@ -710,7 +710,7 @@ void MachOWriter::InitMem(const Constant *C, uintptr_t Offset,
ScatteredOffset));
ScatteredOffset = 0;
} else
LLVM_UNREACHABLE("Unknown constant pointer type!");
llvm_unreachable("Unknown constant pointer type!");
break;
default:
std::string msg;
@ -733,7 +733,7 @@ void MachOWriter::InitMem(const Constant *C, uintptr_t Offset,
PA+SL->getElementOffset(i)));
} else {
cerr << "Bad Type: " << *PC->getType() << "\n";
LLVM_UNREACHABLE("Unknown constant type to initialize memory with!");
llvm_unreachable("Unknown constant type to initialize memory with!");
}
}
}
@ -749,7 +749,7 @@ MachOSym::MachOSym(const GlobalValue *gv, std::string name, uint8_t sect,
switch (GV->getLinkage()) {
default:
LLVM_UNREACHABLE("Unexpected linkage type!");
llvm_unreachable("Unexpected linkage type!");
break;
case GlobalValue::WeakAnyLinkage:
case GlobalValue::WeakODRLinkage:

4
lib/CodeGen/MachineInstr.cpp
View File

@ -157,7 +157,7 @@ bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
return false;
switch (getType()) {
default: LLVM_UNREACHABLE("Unrecognized operand type");
default: llvm_unreachable("Unrecognized operand type");
case MachineOperand::MO_Register:
return getReg() == Other.getReg() && isDef() == Other.isDef() &&
getSubReg() == Other.getSubReg();
@ -275,7 +275,7 @@ void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
OS << '>';
break;
default:
LLVM_UNREACHABLE("Unrecognized operand type");
llvm_unreachable("Unrecognized operand type");
}
if (unsigned TF = getTargetFlags())

2
lib/CodeGen/MachineModuleInfo.cpp
View File

@ -291,7 +291,7 @@ unsigned MachineModuleInfo::getPersonalityIndex() const {
}
// This should never happen
LLVM_UNREACHABLE("Personality function should be set!");
llvm_unreachable("Personality function should be set!");
return 0;
}

2
lib/CodeGen/PostRASchedulerList.cpp
View File

@ -794,7 +794,7 @@ void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) {
cerr << "*** Scheduling failed! ***\n";
SuccSU->dump(this);
cerr << " has been released too many times!\n";
llvm_unreachable();
llvm_unreachable(0);
}
#endif

2
lib/CodeGen/PseudoSourceValue.cpp
View File

@ -84,7 +84,7 @@ bool PseudoSourceValue::isConstant(const MachineFrameInfo *) const {
this == getConstantPool() ||
this == getJumpTable())
return true;
LLVM_UNREACHABLE("Unknown PseudoSourceValue!");
llvm_unreachable("Unknown PseudoSourceValue!");
return false;
}

2
lib/CodeGen/RegAllocLinearScan.cpp
View File

@ -237,7 +237,7 @@ namespace {
}
}
if (Error)
llvm_unreachable();
llvm_unreachable(0);
#endif
regUse_.clear();
regUseBackUp_.clear();

50
lib/CodeGen/SelectionDAG/CallingConvLower.cpp
View File

@ -67,11 +67,11 @@ void CCState::AnalyzeFormalArguments(SDNode *TheArgs, CCAssignFn Fn) {
ISD::ArgFlagsTy ArgFlags =
cast<ARG_FLAGSSDNode>(TheArgs->getOperand(3+i))->getArgFlags();
if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
std::string msg;
raw_string_ostream Msg(msg);
Msg << "Formal argument #" << i << " has unhandled type "
#ifndef NDEBUG
cerr << "Formal argument #" << i << " has unhandled type "
<< ArgVT.getMVTString();
llvm_report_error(Msg.str());
#endif
llvm_unreachable(0);
}
}
}
@ -84,12 +84,12 @@ void CCState::AnalyzeReturn(SDNode *TheRet, CCAssignFn Fn) {
MVT VT = TheRet->getOperand(i*2+1).getValueType();
ISD::ArgFlagsTy ArgFlags =
cast<ARG_FLAGSSDNode>(TheRet->getOperand(i*2+2))->getArgFlags();
if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)){
std::string msg;
raw_string_ostream Msg(msg);
Msg << "Return operand #" << i << " has unhandled type "
if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) {
#ifndef NDEBUG
cerr << "Return operand #" << i << " has unhandled type "
<< VT.getMVTString();
llvm_report_error(Msg.str());
#endif
llvm_unreachable(0);
}
}
}
@ -103,11 +103,11 @@ void CCState::AnalyzeCallOperands(CallSDNode *TheCall, CCAssignFn Fn) {
MVT ArgVT = TheCall->getArg(i).getValueType();
ISD::ArgFlagsTy ArgFlags = TheCall->getArgFlags(i);
if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
std::string msg;
raw_string_ostream Msg(msg);
Msg << "Call operand #" << i << " has unhandled type "
#ifndef NDEBUG
cerr << "Call operand #" << i << " has unhandled type "
<< ArgVT.getMVTString();
llvm_report_error(Msg.str());
#endif
llvm_unreachable(0);
}
}
}
@ -122,11 +122,11 @@ void CCState::AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs,
MVT ArgVT = ArgVTs[i];
ISD::ArgFlagsTy ArgFlags = Flags[i];
if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
std::string msg;
raw_string_ostream Msg(msg);
Msg << "Call operand #" << i << " has unhandled type "
#ifndef NDEBUG
cerr << "Call operand #" << i << " has unhandled type "
<< ArgVT.getMVTString();
llvm_report_error(Msg.str());
#endif
llvm_unreachable(0);
}
}
}
@ -140,11 +140,11 @@ void CCState::AnalyzeCallResult(CallSDNode *TheCall, CCAssignFn Fn) {
if (TheCall->isInreg())
Flags.setInReg();
if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this)) {
std::string msg;
raw_string_ostream Msg(msg);
Msg << "Call result #" << i << " has unhandled type "
#ifndef NDEBUG
cerr << "Call result #" << i << " has unhandled type "
<< VT.getMVTString();
llvm_report_error(Msg.str());
#endif
llvm_unreachable(0);
}
}
}
@ -153,10 +153,10 @@ void CCState::AnalyzeCallResult(CallSDNode *TheCall, CCAssignFn Fn) {
/// produce a single value.
void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) {
if (Fn(0, VT, VT, CCValAssign::Full, ISD::ArgFlagsTy(), *this)) {
std::string msg;
raw_string_ostream Msg(msg);
Msg << "Call result has unhandled type "
#ifndef NDEBUG
cerr << "Call result has unhandled type "
<< VT.getMVTString();
llvm_report_error(Msg.str());
#endif
llvm_unreachable(0);
}
}

8
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -393,7 +393,7 @@ static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
switch (Op.getOpcode()) {
default: LLVM_UNREACHABLE("Unknown code");
default: llvm_unreachable("Unknown code");
case ISD::ConstantFP: {
APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
V.changeSign();
@ -2259,7 +2259,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
switch (N0.getOpcode()) {
default:
LLVM_UNREACHABLE("Unhandled SetCC Equivalent!");
llvm_unreachable("Unhandled SetCC Equivalent!");
case ISD::SETCC:
return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
case ISD::SELECT_CC:
@ -5063,7 +5063,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
if (Value.getOpcode() != ISD::TargetConstantFP) {
SDValue Tmp;
switch (CFP->getValueType(0).getSimpleVT()) {
default: LLVM_UNREACHABLE("Unknown FP type");
default: llvm_unreachable("Unknown FP type");
case MVT::f80: // We don't do this for these yet.
case MVT::f128:
case MVT::ppcf128:
@ -6107,7 +6107,7 @@ bool DAGCombiner::FindAliasInfo(SDNode *N,
SrcValue = ST->getSrcValue();
SrcValueOffset = ST->getSrcValueOffset();
} else {
LLVM_UNREACHABLE("FindAliasInfo expected a memory operand");
llvm_unreachable("FindAliasInfo expected a memory operand");
}
return false;

32
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -949,7 +949,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
#ifndef NDEBUG
cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
#endif
LLVM_UNREACHABLE("Do not know how to legalize this operator!");
llvm_unreachable("Do not know how to legalize this operator!");
case ISD::CALL:
// The only option for this is to custom lower it.
Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
@ -983,7 +983,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
return Tmp2;
case ISD::BUILD_VECTOR:
switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
default: LLVM_UNREACHABLE("This action is not supported yet!");
default: llvm_unreachable("This action is not supported yet!");
case TargetLowering::Custom:
Tmp3 = TLI.LowerOperation(Result, DAG);
if (Tmp3.getNode()) {
@ -1100,7 +1100,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
Tmp4 = Result.getValue(1);
switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
default: LLVM_UNREACHABLE("This action is not supported yet!");
default: llvm_unreachable("This action is not supported yet!");
case TargetLowering::Legal:
// If this is an unaligned load and the target doesn't support it,
// expand it.
@ -1270,7 +1270,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
Tmp2 = LegalizeOp(Ch);
} else {
switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
default: LLVM_UNREACHABLE("This action is not supported yet!");
default: llvm_unreachable("This action is not supported yet!");
case TargetLowering::Custom:
isCustom = true;
// FALLTHROUGH
@ -1363,7 +1363,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
MVT VT = Tmp3.getValueType();
switch (TLI.getOperationAction(ISD::STORE, VT)) {
default: LLVM_UNREACHABLE("This action is not supported yet!");
default: llvm_unreachable("This action is not supported yet!");
case TargetLowering::Legal:
// If this is an unaligned store and the target doesn't support it,
// expand it.
@ -1463,7 +1463,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
ST->getOffset());
switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
default: LLVM_UNREACHABLE("This action is not supported yet!");
default: llvm_unreachable("This action is not supported yet!");
case TargetLowering::Legal:
// If this is an unaligned store and the target doesn't support it,
// expand it.
@ -1691,7 +1691,7 @@ void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
MVT OpVT = LHS.getValueType();
ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
switch (TLI.getCondCodeAction(CCCode, OpVT)) {
default: LLVM_UNREACHABLE("Unknown condition code action!");
default: llvm_unreachable("Unknown condition code action!");
case TargetLowering::Legal:
// Nothing to do.
break;
@ -1699,7 +1699,7 @@ void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
unsigned Opc = 0;
switch (CCCode) {
default: LLVM_UNREACHABLE("Don't know how to expand this condition!");
default: llvm_unreachable("Don't know how to expand this condition!");
case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
@ -1926,7 +1926,7 @@ SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
RTLIB::Libcall Call_PPCF128) {
RTLIB::Libcall LC;
switch (Node->getValueType(0).getSimpleVT()) {
default: LLVM_UNREACHABLE("Unexpected request for libcall!");
default: llvm_unreachable("Unexpected request for libcall!");
case MVT::f32: LC = Call_F32; break;
case MVT::f64: LC = Call_F64; break;
case MVT::f80: LC = Call_F80; break;
@ -1942,7 +1942,7 @@ SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
RTLIB::Libcall Call_I128) {
RTLIB::Libcall LC;
switch (Node->getValueType(0).getSimpleVT()) {
default: LLVM_UNREACHABLE("Unexpected request for libcall!");
default: llvm_unreachable("Unexpected request for libcall!");
case MVT::i16: LC = Call_I16; break;
case MVT::i32: LC = Call_I32; break;
case MVT::i64: LC = Call_I64; break;
@ -2028,7 +2028,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
// offset depending on the data type.
uint64_t FF;
switch (Op0.getValueType().getSimpleVT()) {
default: LLVM_UNREACHABLE("Unsupported integer type!");
default: llvm_unreachable("Unsupported integer type!");
case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
@ -2147,7 +2147,7 @@ SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
MVT SHVT = TLI.getShiftAmountTy();
SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
switch (VT.getSimpleVT()) {
default: LLVM_UNREACHABLE("Unhandled Expand type in BSWAP!");
default: llvm_unreachable("Unhandled Expand type in BSWAP!");
case MVT::i16:
Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
@ -2192,7 +2192,7 @@ SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
DebugLoc dl) {
switch (Opc) {
default: LLVM_UNREACHABLE("Cannot expand this yet!");
default: llvm_unreachable("Cannot expand this yet!");
case ISD::CTPOP: {
static const uint64_t mask[6] = {
0x5555555555555555ULL, 0x3333333333333333ULL,
@ -2306,7 +2306,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
else if (VT.isFloatingPoint())
Results.push_back(DAG.getConstantFP(0, VT));
else
LLVM_UNREACHABLE("Unknown value type!");
llvm_unreachable("Unknown value type!");
break;
}
case ISD::TRAP: {
@ -2810,7 +2810,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
// type in some cases cases.
// Also, we can fall back to a division in some cases, but that's a big
// performance hit in the general case.
LLVM_UNREACHABLE("Don't know how to expand this operation yet!");
llvm_unreachable("Don't know how to expand this operation yet!");
}
if (isSigned) {
Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy());
@ -3102,7 +3102,7 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node,
break;
}
if (NewInTy.isInteger())
LLVM_UNREACHABLE("Cannot promote Legal Integer SETCC yet");
llvm_unreachable("Cannot promote Legal Integer SETCC yet");
else {
Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp1);
Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp2);

8
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
View File

@ -53,7 +53,7 @@ void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
cerr << "SoftenFloatResult #" << ResNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
LLVM_UNREACHABLE("Do not know how to soften the result of this operator!");
llvm_unreachable("Do not know how to soften the result of this operator!");
case ISD::BIT_CONVERT: R = SoftenFloatRes_BIT_CONVERT(N); break;
case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break;
@ -541,7 +541,7 @@ bool DAGTypeLegalizer::SoftenFloatOperand(SDNode *N, unsigned OpNo) {
cerr << "SoftenFloatOperand Op #" << OpNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
LLVM_UNREACHABLE("Do not know how to soften this operator's operand!");
llvm_unreachable("Do not know how to soften this operator's operand!");
case ISD::BIT_CONVERT: Res = SoftenFloatOp_BIT_CONVERT(N); break;
case ISD::BR_CC: Res = SoftenFloatOp_BR_CC(N); break;
@ -781,7 +781,7 @@ void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) {
cerr << "ExpandFloatResult #" << ResNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
LLVM_UNREACHABLE("Do not know how to expand the result of this operator!");
llvm_unreachable("Do not know how to expand the result of this operator!");
case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
@ -1180,7 +1180,7 @@ bool DAGTypeLegalizer::ExpandFloatOperand(SDNode *N, unsigned OpNo) {
cerr << "ExpandFloatOperand Op #" << OpNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
LLVM_UNREACHABLE("Do not know how to expand this operator's operand!");
llvm_unreachable("Do not know how to expand this operator's operand!");
case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;

22
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -45,7 +45,7 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
cerr << "PromoteIntegerResult #" << ResNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
LLVM_UNREACHABLE("Do not know how to promote this operator!");
llvm_unreachable("Do not know how to promote this operator!");
case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break;
@ -491,7 +491,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
SDValue Res;
switch (getTypeAction(N->getOperand(0).getValueType())) {
default: LLVM_UNREACHABLE("Unknown type action!");
default: llvm_unreachable("Unknown type action!");
case Legal:
case ExpandInteger:
Res = N->getOperand(0);
@ -610,7 +610,7 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
LLVM_UNREACHABLE("Do not know how to promote this operator's operand!");
llvm_unreachable("Do not know how to promote this operator's operand!");
case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break;
@ -666,7 +666,7 @@ void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
// insert sign extends for ALL conditions, but zero extend is cheaper on
// many machines (an AND instead of two shifts), so prefer it.
switch (CCCode) {
default: LLVM_UNREACHABLE("Unknown integer comparison!");
default: llvm_unreachable("Unknown integer comparison!");
case ISD::SETEQ:
case ISD::SETNE:
case ISD::SETUGE:
@ -923,7 +923,7 @@ void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
cerr << "ExpandIntegerResult #" << ResNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
LLVM_UNREACHABLE("Do not know how to expand the result of this operator!");
llvm_unreachable("Do not know how to expand the result of this operator!");
case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
@ -1104,7 +1104,7 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
DAG.getConstant(~HighBitMask, ShTy));
switch (N->getOpcode()) {
default: LLVM_UNREACHABLE("Unknown shift");
default: llvm_unreachable("Unknown shift");
case ISD::SHL:
Lo = DAG.getConstant(0, NVT); // Low part is zero.
Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
@ -1132,7 +1132,7 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
Amt);
unsigned Op1, Op2;
switch (N->getOpcode()) {
default: LLVM_UNREACHABLE("Unknown shift");
default: llvm_unreachable("Unknown shift");
case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
case ISD::SRL:
case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
@ -1172,7 +1172,7 @@ ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
SDValue Lo1, Hi1, Lo2, Hi2;
switch (N->getOpcode()) {
default: LLVM_UNREACHABLE("Unknown shift");
default: llvm_unreachable("Unknown shift");
case ISD::SHL:
// ShAmt < NVTBits
Lo1 = DAG.getConstant(0, NVT); // Low part is zero.
@ -1792,7 +1792,7 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
}
if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
LLVM_UNREACHABLE("Unsupported shift!");
llvm_unreachable("Unsupported shift!");
}
void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
@ -1968,7 +1968,7 @@ bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
LLVM_UNREACHABLE("Do not know how to expand this operator's operand!");
llvm_unreachable("Do not know how to expand this operator's operand!");
case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
@ -2050,7 +2050,7 @@ void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
// FIXME: This generated code sucks.
ISD::CondCode LowCC;
switch (CCCode) {
default: LLVM_UNREACHABLE("Unknown integer setcc!");
default: llvm_unreachable("Unknown integer setcc!");
case ISD::SETLT:
case ISD::SETULT: LowCC = ISD::SETULT; break;
case ISD::SETGT:

4
lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
View File

@ -150,7 +150,7 @@ void DAGTypeLegalizer::PerformExpensiveChecks() {
if (Mapped & 128)
cerr << " WidenedVectors";
cerr << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
}
}
@ -432,7 +432,7 @@ NodeDone:
if (Failed) {
I->dump(&DAG); cerr << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
}
#endif

16
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -41,7 +41,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
cerr << "ScalarizeVectorResult #" << ResNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
LLVM_UNREACHABLE("Do not know how to scalarize the result of this operator!");
llvm_unreachable("Do not know how to scalarize the result of this operator!");
case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break;
case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
@ -278,7 +278,7 @@ bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
cerr << "ScalarizeVectorOperand Op #" << OpNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
LLVM_UNREACHABLE("Do not know how to scalarize this operator's operand!");
llvm_unreachable("Do not know how to scalarize this operator's operand!");
case ISD::BIT_CONVERT:
Res = ScalarizeVecOp_BIT_CONVERT(N);
break;
@ -378,7 +378,7 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
cerr << "SplitVectorResult #" << ResNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
LLVM_UNREACHABLE("Do not know how to split the result of this operator!");
llvm_unreachable("Do not know how to split the result of this operator!");
case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
@ -576,7 +576,7 @@ void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
SDValue VLo, VHi;
MVT InVT = N->getOperand(0).getValueType();
switch (getTypeAction(InVT)) {
default: LLVM_UNREACHABLE("Unexpected type action!");
default: llvm_unreachable("Unexpected type action!");
case Legal: {
MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
LoVT.getVectorNumElements());
@ -768,7 +768,7 @@ void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
// Split the input.
MVT InVT = N->getOperand(0).getValueType();
switch (getTypeAction(InVT)) {
default: LLVM_UNREACHABLE("Unexpected type action!");
default: llvm_unreachable("Unexpected type action!");
case Legal: {
MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
LoVT.getVectorNumElements());
@ -928,7 +928,7 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
cerr << "SplitVectorOperand Op #" << OpNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
LLVM_UNREACHABLE("Do not know how to split this operator's operand!");
llvm_unreachable("Do not know how to split this operator's operand!");
case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break;
case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
@ -1117,7 +1117,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
cerr << "WidenVectorResult #" << ResNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
LLVM_UNREACHABLE("Do not know how to widen the result of this operator!");
llvm_unreachable("Do not know how to widen the result of this operator!");
case ISD::BIT_CONVERT: Res = WidenVecRes_BIT_CONVERT(N); break;
case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
@ -1773,7 +1773,7 @@ bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) {
cerr << "WidenVectorOperand op #" << ResNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
LLVM_UNREACHABLE("Do not know how to widen this operator's operand!");
llvm_unreachable("Do not know how to widen this operator's operand!");
case ISD::BIT_CONVERT: Res = WidenVecOp_BIT_CONVERT(N); break;
case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;

4
lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
View File

@ -140,7 +140,7 @@ void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) {
cerr << "*** Scheduling failed! ***\n";
PredSU->dump(this);
cerr << " has been released too many times!\n";
llvm_unreachable();
llvm_unreachable(0);
}
#endif
@ -569,7 +569,7 @@ void ScheduleDAGFast::ListScheduleBottomUp() {
}
if (!CurSU) {
LLVM_UNREACHABLE("Unable to resolve live physical register dependencies!");
llvm_unreachable("Unable to resolve live physical register dependencies!");
}
}

2
lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
View File

@ -114,7 +114,7 @@ void ScheduleDAGList::ReleaseSucc(SUnit *SU, const SDep &D) {
cerr << "*** Scheduling failed! ***\n";
SuccSU->dump(this);
cerr << " has been released too many times!\n";
llvm_unreachable();
llvm_unreachable(0);
}
#endif

4
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
View File

@ -203,7 +203,7 @@ void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) {
cerr << "*** Scheduling failed! ***\n";
PredSU->dump(this);
cerr << " has been released too many times!\n";
llvm_unreachable();
llvm_unreachable(0);
}
#endif
@ -830,7 +830,7 @@ void ScheduleDAGRRList::ReleaseSucc(SUnit *SU, const SDep *SuccEdge) {
cerr << "*** Scheduling failed! ***\n";
SuccSU->dump(this);
cerr << " has been released too many times!\n";
llvm_unreachable();
llvm_unreachable(0);
}
#endif

8
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
View File

@ -431,7 +431,7 @@ void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
MI->addOperand(MachineOperand::CreateImm(SubIdx));
BB->insert(InsertPos, MI);
} else
LLVM_UNREACHABLE("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
SDValue Op(Node, 0);
bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
@ -552,10 +552,10 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
#ifndef NDEBUG
Node->dump(DAG);
#endif
LLVM_UNREACHABLE("This target-independent node should have been selected!");
llvm_unreachable("This target-independent node should have been selected!");
break;
case ISD::EntryToken:
LLVM_UNREACHABLE("EntryToken should have been excluded from the schedule!");
llvm_unreachable("EntryToken should have been excluded from the schedule!");
break;
case ISD::TokenFactor: // fall thru
break;
@ -619,7 +619,7 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
++i; // Skip the ID value.
switch (Flags & 7) {
default: LLVM_UNREACHABLE("Bad flags!");
default: llvm_unreachable("Bad flags!");
case 2: // Def of register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();

22
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -54,7 +54,7 @@ static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) {
static const fltSemantics *MVTToAPFloatSemantics(MVT VT) {
switch (VT.getSimpleVT()) {
default: LLVM_UNREACHABLE("Unknown FP format");
default: llvm_unreachable("Unknown FP format");
case MVT::f32: return &APFloat::IEEEsingle;
case MVT::f64: return &APFloat::IEEEdouble;
case MVT::f80: return &APFloat::x87DoubleExtended;
@ -244,7 +244,7 @@ ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) {
/// if the operation does not depend on the sign of the input (setne and seteq).
static int isSignedOp(ISD::CondCode Opcode) {
switch (Opcode) {
default: LLVM_UNREACHABLE("Illegal integer setcc operation!");
default: llvm_unreachable("Illegal integer setcc operation!");
case ISD::SETEQ:
case ISD::SETNE: return 0;
case ISD::SETLT:
@ -364,7 +364,7 @@ static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) {
switch (N->getOpcode()) {
case ISD::TargetExternalSymbol:
case ISD::ExternalSymbol:
LLVM_UNREACHABLE("Should only be used on nodes with operands");
llvm_unreachable("Should only be used on nodes with operands");
default: break; // Normal nodes don't need extra info.
case ISD::ARG_FLAGS:
ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits());
@ -627,7 +627,7 @@ bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) {
bool Erased = false;
switch (N->getOpcode()) {
case ISD::EntryToken:
LLVM_UNREACHABLE("EntryToken should not be in CSEMaps!");
llvm_unreachable("EntryToken should not be in CSEMaps!");
return false;
case ISD::HANDLENODE: return false; // noop.
case ISD::CONDCODE:
@ -669,7 +669,7 @@ bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) {
!N->isMachineOpcode() && !doNotCSE(N)) {
N->dump(this);
cerr << "\n";
LLVM_UNREACHABLE("Node is not in map!");
llvm_unreachable("Node is not in map!");
}
#endif
return Erased;
@ -1443,7 +1443,7 @@ SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1,
const APInt &C1 = N1C->getAPIntValue();
switch (Cond) {
default: LLVM_UNREACHABLE("Unknown integer setcc!");
default: llvm_unreachable("Unknown integer setcc!");
case ISD::SETEQ: return getConstant(C1 == C2, VT);
case ISD::SETNE: return getConstant(C1 != C2, VT);
case ISD::SETULT: return getConstant(C1.ult(C2), VT);
@ -2372,7 +2372,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
case ISD::MERGE_VALUES:
case ISD::CONCAT_VECTORS:
return Operand; // Factor, merge or concat of one node? No need.
case ISD::FP_ROUND: LLVM_UNREACHABLE("Invalid method to make FP_ROUND node");
case ISD::FP_ROUND: llvm_unreachable("Invalid method to make FP_ROUND node");
case ISD::FP_EXTEND:
assert(VT.isFloatingPoint() &&
Operand.getValueType().isFloatingPoint() && "Invalid FP cast!");
@ -2947,7 +2947,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
}
break;
case ISD::VECTOR_SHUFFLE:
LLVM_UNREACHABLE("should use getVectorShuffle constructor!");
llvm_unreachable("should use getVectorShuffle constructor!");
break;
case ISD::BIT_CONVERT:
// Fold bit_convert nodes from a type to themselves.
@ -4061,7 +4061,7 @@ SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4) {
SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) {
switch (NumVTs) {
case 0: LLVM_UNREACHABLE("Cannot have nodes without results!");
case 0: llvm_unreachable("Cannot have nodes without results!");
case 1: return getVTList(VTs[0]);
case 2: return getVTList(VTs[0], VTs[1]);
case 3: return getVTList(VTs[0], VTs[1], VTs[2]);
@ -5342,7 +5342,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::CONVERT_RNDSAT: {
switch (cast<CvtRndSatSDNode>(this)->getCvtCode()) {
default: LLVM_UNREACHABLE("Unknown cvt code!");
default: llvm_unreachable("Unknown cvt code!");
case ISD::CVT_FF: return "cvt_ff";
case ISD::CVT_FS: return "cvt_fs";
case ISD::CVT_FU: return "cvt_fu";
@ -5394,7 +5394,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::CONDCODE:
switch (cast<CondCodeSDNode>(this)->get()) {
default: LLVM_UNREACHABLE("Unknown setcc condition!");
default: llvm_unreachable("Unknown setcc condition!");
case ISD::SETOEQ: return "setoeq";
case ISD::SETOGT: return "setogt";
case ISD::SETOGE: return "setoge";

18
lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
View File

@ -556,7 +556,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
LLVM_UNREACHABLE("Unknown mismatch!");
llvm_unreachable("Unknown mismatch!");
return SDValue();
}
@ -592,7 +592,7 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
ValueVT = MVT::getIntegerVT(NumParts * PartBits);
Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
} else {
LLVM_UNREACHABLE("Unknown mismatch!");
llvm_unreachable("Unknown mismatch!");
}
} else if (PartBits == ValueVT.getSizeInBits()) {
// Different types of the same size.
@ -604,7 +604,7 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
ValueVT = MVT::getIntegerVT(NumParts * PartBits);
Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
} else {
LLVM_UNREACHABLE("Unknown mismatch!");
llvm_unreachable("Unknown mismatch!");
}
}
@ -818,7 +818,7 @@ void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
// Note: this doesn't use InstVisitor, because it has to work with
// ConstantExpr's in addition to instructions.
switch (Opcode) {
default: LLVM_UNREACHABLE("Unknown instruction type encountered!");
default: llvm_unreachable("Unknown instruction type encountered!");
// Build the switch statement using the Instruction.def file.
#define HANDLE_INST(NUM, OPCODE, CLASS) \
case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
@ -1073,7 +1073,7 @@ static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
default:
LLVM_UNREACHABLE("Invalid FCmp predicate opcode!");
llvm_unreachable("Invalid FCmp predicate opcode!");
FOC = FPC = ISD::SETFALSE;
break;
}
@ -1099,7 +1099,7 @@ static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
case ICmpInst::ICMP_SGT: return ISD::SETGT;
case ICmpInst::ICMP_UGT: return ISD::SETUGT;
default:
LLVM_UNREACHABLE("Invalid ICmp predicate opcode!");
llvm_unreachable("Invalid ICmp predicate opcode!");
return ISD::SETNE;
}
}
@ -1131,7 +1131,7 @@ SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
Condition = getFCmpCondCode(FC->getPredicate());
} else {
Condition = ISD::SETEQ; // silence warning.
LLVM_UNREACHABLE("Unknown compare instruction");
llvm_unreachable("Unknown compare instruction");
}
CaseBlock CB(Condition, BOp->getOperand(0),
@ -4256,7 +4256,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
case Intrinsic::gcread:
case Intrinsic::gcwrite:
LLVM_UNREACHABLE("GC failed to lower gcread/gcwrite intrinsics!");
llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
return 0;
case Intrinsic::flt_rounds: {
@ -5763,7 +5763,7 @@ void TargetLowering::LowerOperationWrapper(SDNode *N,
}
SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
LLVM_UNREACHABLE("LowerOperation not implemented for this target!");
llvm_unreachable("LowerOperation not implemented for this target!");
return SDValue();
}

4
lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
View File

@ -540,10 +540,10 @@ private:
void visitVACopy(CallInst &I);
void visitUserOp1(Instruction &I) {
LLVM_UNREACHABLE("UserOp1 should not exist at instruction selection time!");
llvm_unreachable("UserOp1 should not exist at instruction selection time!");
}
void visitUserOp2(Instruction &I) {
LLVM_UNREACHABLE("UserOp2 should not exist at instruction selection time!");
llvm_unreachable("UserOp2 should not exist at instruction selection time!");
}
const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op);

4
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -157,7 +157,7 @@ MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
"'usesCustomDAGSchedInserter', it must implement "
"TargetLowering::EmitInstrWithCustomInserter!";
#endif
llvm_unreachable();
llvm_unreachable(0);
return 0;
}
@ -878,7 +878,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
if (EnableFastISelAbort)
// The "fast" selector couldn't handle something and bailed.
// For the purpose of debugging, just abort.
LLVM_UNREACHABLE("FastISel didn't select the entire block");
llvm_unreachable("FastISel didn't select the entire block");
}
break;
}

6
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -1841,7 +1841,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
if (CFP->getValueAPF().isNaN()) {
// If an operand is known to be a nan, we can fold it.
switch (ISD::getUnorderedFlavor(Cond)) {
default: LLVM_UNREACHABLE("Unknown flavor!");
default: llvm_unreachable("Unknown flavor!");
case 0: // Known false.
return DAG.getConstant(0, VT);
case 1: // Known true.
@ -2001,7 +2001,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
SDValue Temp;
if (N0.getValueType() == MVT::i1 && foldBooleans) {
switch (Cond) {
default: LLVM_UNREACHABLE("Unknown integer setcc!");
default: llvm_unreachable("Unknown integer setcc!");
case ISD::SETEQ: // X == Y -> ~(X^Y)
Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
N0 = DAG.getNOT(dl, Temp, MVT::i1);
@ -2311,7 +2311,7 @@ unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
/// is.
static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
switch (CT) {
default: LLVM_UNREACHABLE("Unknown constraint type!");
default: llvm_unreachable("Unknown constraint type!");
case TargetLowering::C_Other:
case TargetLowering::C_Unknown:
return 0;

4
lib/CodeGen/SimpleRegisterCoalescing.cpp
View File

@ -1345,7 +1345,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
DstSubIdx = CopyMI->getOperand(3).getImm();
SrcReg = CopyMI->getOperand(2).getReg();
} else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)){
LLVM_UNREACHABLE("Unrecognized copy instruction!");
llvm_unreachable("Unrecognized copy instruction!");
}
// If they are already joined we continue.
@ -2062,7 +2062,7 @@ bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
*tri_->getSuperRegisters(LHS.reg))
// Imprecise sub-register information. Can't handle it.
return false;
LLVM_UNREACHABLE("No copies from the RHS?");
llvm_unreachable("No copies from the RHS?");
} else {
LHSValNo = EliminatedLHSVals[0];
}

8
lib/CodeGen/VirtRegRewriter.cpp
View File

@ -1000,7 +1000,7 @@ private:
// Unfold current MI.
SmallVector<MachineInstr*, 4> NewMIs;
if (!TII->unfoldMemoryOperand(MF, &MI, VirtReg, false, false, NewMIs))
LLVM_UNREACHABLE("Unable unfold the load / store folding instruction!");
llvm_unreachable("Unable unfold the load / store folding instruction!");
assert(NewMIs.size() == 1);
AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg);
VRM.transferRestorePts(&MI, NewMIs[0]);
@ -1016,7 +1016,7 @@ private:
NextMII = next(NextMII);
NewMIs.clear();
if (!TII->unfoldMemoryOperand(MF, &NextMI, VirtReg, false, false, NewMIs))
LLVM_UNREACHABLE("Unable unfold the load / store folding instruction!");
llvm_unreachable("Unable unfold the load / store folding instruction!");
assert(NewMIs.size() == 1);
AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg);
VRM.transferRestorePts(&NextMI, NewMIs[0]);
@ -1452,7 +1452,7 @@ private:
assert(RC && "Unable to determine register class!");
int SS = VRM.getEmergencySpillSlot(RC);
if (UsedSS.count(SS))
LLVM_UNREACHABLE("Need to spill more than one physical registers!");
llvm_unreachable("Need to spill more than one physical registers!");
UsedSS.insert(SS);
TII->storeRegToStackSlot(MBB, MII, PhysReg, true, SS, RC);
MachineInstr *StoreMI = prior(MII);
@ -2177,7 +2177,7 @@ private:
llvm::VirtRegRewriter* llvm::createVirtRegRewriter() {
switch (RewriterOpt) {
default: LLVM_UNREACHABLE("Unreachable!");
default: llvm_unreachable("Unreachable!");
case local:
return new LocalRewriter();
case trivial:

18
lib/ExecutionEngine/ExecutionEngine.cpp
View File

@ -421,7 +421,7 @@ void *ExecutionEngine::getPointerToGlobal(const GlobalValue *GV) {
const_cast<GlobalVariable *>(dyn_cast<GlobalVariable>(GV)))
EmitGlobalVariable(GVar);
else
LLVM_UNREACHABLE("Global hasn't had an address allocated yet!");
llvm_unreachable("Global hasn't had an address allocated yet!");
return state.getGlobalAddressMap(locked)[GV];
}
@ -548,7 +548,7 @@ GenericValue ExecutionEngine::getConstantValue(const Constant *C) {
GenericValue GV = getConstantValue(Op0);
const Type* DestTy = CE->getType();
switch (Op0->getType()->getTypeID()) {
default: LLVM_UNREACHABLE("Invalid bitcast operand");
default: llvm_unreachable("Invalid bitcast operand");
case Type::IntegerTyID:
assert(DestTy->isFloatingPoint() && "invalid bitcast");
if (DestTy == Type::FloatTy)
@ -587,10 +587,10 @@ GenericValue ExecutionEngine::getConstantValue(const Constant *C) {
GenericValue RHS = getConstantValue(CE->getOperand(1));
GenericValue GV;
switch (CE->getOperand(0)->getType()->getTypeID()) {
default: LLVM_UNREACHABLE("Bad add type!");
default: llvm_unreachable("Bad add type!");
case Type::IntegerTyID:
switch (CE->getOpcode()) {
default: LLVM_UNREACHABLE("Invalid integer opcode");
default: llvm_unreachable("Invalid integer opcode");
case Instruction::Add: GV.IntVal = LHS.IntVal + RHS.IntVal; break;
case Instruction::Sub: GV.IntVal = LHS.IntVal - RHS.IntVal; break;
case Instruction::Mul: GV.IntVal = LHS.IntVal * RHS.IntVal; break;
@ -605,7 +605,7 @@ GenericValue ExecutionEngine::getConstantValue(const Constant *C) {
break;
case Type::FloatTyID:
switch (CE->getOpcode()) {
default: LLVM_UNREACHABLE("Invalid float opcode");
default: llvm_unreachable("Invalid float opcode");
case Instruction::FAdd:
GV.FloatVal = LHS.FloatVal + RHS.FloatVal; break;
case Instruction::FSub:
@ -620,7 +620,7 @@ GenericValue ExecutionEngine::getConstantValue(const Constant *C) {
break;
case Type::DoubleTyID:
switch (CE->getOpcode()) {
default: LLVM_UNREACHABLE("Invalid double opcode");
default: llvm_unreachable("Invalid double opcode");
case Instruction::FAdd:
GV.DoubleVal = LHS.DoubleVal + RHS.DoubleVal; break;
case Instruction::FSub:
@ -638,7 +638,7 @@ GenericValue ExecutionEngine::getConstantValue(const Constant *C) {
case Type::FP128TyID: {
APFloat apfLHS = APFloat(LHS.IntVal);
switch (CE->getOpcode()) {
default: LLVM_UNREACHABLE("Invalid long double opcode");llvm_unreachable();
default: llvm_unreachable("Invalid long double opcode");llvm_unreachable(0);
case Instruction::FAdd:
apfLHS.add(APFloat(RHS.IntVal), APFloat::rmNearestTiesToEven);
GV.IntVal = apfLHS.bitcastToAPInt();
@ -698,7 +698,7 @@ GenericValue ExecutionEngine::getConstantValue(const Constant *C) {
else if (const GlobalVariable* GV = dyn_cast<GlobalVariable>(C))
Result = PTOGV(getOrEmitGlobalVariable(const_cast<GlobalVariable*>(GV)));
else
LLVM_UNREACHABLE("Unknown constant pointer type!");
llvm_unreachable("Unknown constant pointer type!");
break;
default:
std::string msg;
@ -881,7 +881,7 @@ void ExecutionEngine::InitializeMemory(const Constant *Init, void *Addr) {
}
cerr << "Bad Type: " << *Init->getType() << "\n";
LLVM_UNREACHABLE("Unknown constant type to initialize memory with!");
llvm_unreachable("Unknown constant type to initialize memory with!");
}
/// EmitGlobals - Emit all of the global variables to memory, storing their

4
lib/ExecutionEngine/ExecutionEngineBindings.cpp
View File

@ -46,7 +46,7 @@ LLVMGenericValueRef LLVMCreateGenericValueOfFloat(LLVMTypeRef TyRef, double N) {
GenVal->DoubleVal = N;
break;
default:
LLVM_UNREACHABLE("LLVMGenericValueToFloat supports only float and double.");
llvm_unreachable("LLVMGenericValueToFloat supports only float and double.");
}
return wrap(GenVal);
}
@ -75,7 +75,7 @@ double LLVMGenericValueToFloat(LLVMTypeRef TyRef, LLVMGenericValueRef GenVal) {
case Type::DoubleTyID:
return unwrap(GenVal)->DoubleVal;
default:
LLVM_UNREACHABLE("LLVMGenericValueToFloat supports only float and double.");
llvm_unreachable("LLVMGenericValueToFloat supports only float and double.");
break;
}
return 0; // Not reached

60
lib/ExecutionEngine/Interpreter/Execution.cpp
View File

@ -58,7 +58,7 @@ static void executeFAddInst(GenericValue &Dest, GenericValue Src1,
IMPLEMENT_BINARY_OPERATOR(+, Double);
default:
cerr << "Unhandled type for FAdd instruction: " << *Ty << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
}
@ -69,7 +69,7 @@ static void executeFSubInst(GenericValue &Dest, GenericValue Src1,
IMPLEMENT_BINARY_OPERATOR(-, Double);
default:
cerr << "Unhandled type for FSub instruction: " << *Ty << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
}
@ -80,7 +80,7 @@ static void executeFMulInst(GenericValue &Dest, GenericValue Src1,
IMPLEMENT_BINARY_OPERATOR(*, Double);
default:
cerr << "Unhandled type for FMul instruction: " << *Ty << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
}
@ -91,7 +91,7 @@ static void executeFDivInst(GenericValue &Dest, GenericValue Src1,
IMPLEMENT_BINARY_OPERATOR(/, Double);
default:
cerr << "Unhandled type for FDiv instruction: " << *Ty << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
}
@ -106,7 +106,7 @@ static void executeFRemInst(GenericValue &Dest, GenericValue Src1,
break;
default:
cerr << "Unhandled type for Rem instruction: " << *Ty << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
}
@ -133,7 +133,7 @@ static GenericValue executeICMP_EQ(GenericValue Src1, GenericValue Src2,
IMPLEMENT_POINTER_ICMP(==);
default:
cerr << "Unhandled type for ICMP_EQ predicate: " << *Ty << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
return Dest;
}
@ -146,7 +146,7 @@ static GenericValue executeICMP_NE(GenericValue Src1, GenericValue Src2,
IMPLEMENT_POINTER_ICMP(!=);
default:
cerr << "Unhandled type for ICMP_NE predicate: " << *Ty << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
return Dest;
}
@ -159,7 +159,7 @@ static GenericValue executeICMP_ULT(GenericValue Src1, GenericValue Src2,
IMPLEMENT_POINTER_ICMP(<);
default:
cerr << "Unhandled type for ICMP_ULT predicate: " << *Ty << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
return Dest;
}
@ -172,7 +172,7 @@ static GenericValue executeICMP_SLT(GenericValue Src1, GenericValue Src2,
IMPLEMENT_POINTER_ICMP(<);
default:
cerr << "Unhandled type for ICMP_SLT predicate: " << *Ty << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
return Dest;
}
@ -185,7 +185,7 @@ static GenericValue executeICMP_UGT(GenericValue Src1, GenericValue Src2,
IMPLEMENT_POINTER_ICMP(>);
default:
cerr << "Unhandled type for ICMP_UGT predicate: " << *Ty << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
return Dest;
}
@ -198,7 +198,7 @@ static GenericValue executeICMP_SGT(GenericValue Src1, GenericValue Src2,
IMPLEMENT_POINTER_ICMP(>);
default:
cerr << "Unhandled type for ICMP_SGT predicate: " << *Ty << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
return Dest;
}
@ -211,7 +211,7 @@ static GenericValue executeICMP_ULE(GenericValue Src1, GenericValue Src2,
IMPLEMENT_POINTER_ICMP(<=);
default:
cerr << "Unhandled type for ICMP_ULE predicate: " << *Ty << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
return Dest;
}
@ -224,7 +224,7 @@ static GenericValue executeICMP_SLE(GenericValue Src1, GenericValue Src2,
IMPLEMENT_POINTER_ICMP(<=);
default:
cerr << "Unhandled type for ICMP_SLE predicate: " << *Ty << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
return Dest;
}
@ -237,7 +237,7 @@ static GenericValue executeICMP_UGE(GenericValue Src1, GenericValue Src2,
IMPLEMENT_POINTER_ICMP(>=);
default:
cerr << "Unhandled type for ICMP_UGE predicate: " << *Ty << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
return Dest;
}
@ -250,7 +250,7 @@ static GenericValue executeICMP_SGE(GenericValue Src1, GenericValue Src2,
IMPLEMENT_POINTER_ICMP(>=);
default:
cerr << "Unhandled type for ICMP_SGE predicate: " << *Ty << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
return Dest;
}
@ -275,7 +275,7 @@ void Interpreter::visitICmpInst(ICmpInst &I) {
case ICmpInst::ICMP_SGE: R = executeICMP_SGE(Src1, Src2, Ty); break;
default:
cerr << "Don't know how to handle this ICmp predicate!\n-->" << I;
llvm_unreachable();
llvm_unreachable(0);
}
SetValue(&I, R, SF);
@ -294,7 +294,7 @@ static GenericValue executeFCMP_OEQ(GenericValue Src1, GenericValue Src2,
IMPLEMENT_FCMP(==, Double);
default:
cerr << "Unhandled type for FCmp EQ instruction: " << *Ty << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
return Dest;
}
@ -308,7 +308,7 @@ static GenericValue executeFCMP_ONE(GenericValue Src1, GenericValue Src2,
default:
cerr << "Unhandled type for FCmp NE instruction: " << *Ty << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
return Dest;
}
@ -321,7 +321,7 @@ static GenericValue executeFCMP_OLE(GenericValue Src1, GenericValue Src2,
IMPLEMENT_FCMP(<=, Double);
default:
cerr << "Unhandled type for FCmp LE instruction: " << *Ty << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
return Dest;
}
@ -334,7 +334,7 @@ static GenericValue executeFCMP_OGE(GenericValue Src1, GenericValue Src2,
IMPLEMENT_FCMP(>=, Double);
default:
cerr << "Unhandled type for FCmp GE instruction: " << *Ty << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
return Dest;
}
@ -347,7 +347,7 @@ static GenericValue executeFCMP_OLT(GenericValue Src1, GenericValue Src2,
IMPLEMENT_FCMP(<, Double);
default:
cerr << "Unhandled type for FCmp LT instruction: " << *Ty << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
return Dest;
}
@ -360,7 +360,7 @@ static GenericValue executeFCMP_OGT(GenericValue Src1, GenericValue Src2,
IMPLEMENT_FCMP(>, Double);
default:
cerr << "Unhandled type for FCmp GT instruction: " << *Ty << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
return Dest;
}
@ -469,7 +469,7 @@ void Interpreter::visitFCmpInst(FCmpInst &I) {
case FCmpInst::FCMP_OGE: R = executeFCMP_OGE(Src1, Src2, Ty); break;
default:
cerr << "Don't know how to handle this FCmp predicate!\n-->" << I;
llvm_unreachable();
llvm_unreachable(0);
}
SetValue(&I, R, SF);
@ -515,7 +515,7 @@ static GenericValue executeCmpInst(unsigned predicate, GenericValue Src1,
}
default:
cerr << "Unhandled Cmp predicate\n";
llvm_unreachable();
llvm_unreachable(0);
}
}
@ -544,7 +544,7 @@ void Interpreter::visitBinaryOperator(BinaryOperator &I) {
case Instruction::Xor: R.IntVal = Src1.IntVal ^ Src2.IntVal; break;
default:
cerr << "Don't know how to handle this binary operator!\n-->" << I;
llvm_unreachable();
llvm_unreachable(0);
}
SetValue(&I, R, SF);
@ -1079,7 +1079,7 @@ GenericValue Interpreter::executeBitCastInst(Value *SrcVal, const Type *DstTy,
} else if (SrcTy->isInteger()) {
Dest.IntVal = Src.IntVal;
} else
LLVM_UNREACHABLE("Invalid BitCast");
llvm_unreachable("Invalid BitCast");
} else if (DstTy == Type::FloatTy) {
if (SrcTy->isInteger())
Dest.FloatVal = Src.IntVal.bitsToFloat();
@ -1091,7 +1091,7 @@ GenericValue Interpreter::executeBitCastInst(Value *SrcVal, const Type *DstTy,
else
Dest.DoubleVal = Src.DoubleVal;
} else
LLVM_UNREACHABLE("Invalid Bitcast");
llvm_unreachable("Invalid Bitcast");
return Dest;
}
@ -1176,7 +1176,7 @@ void Interpreter::visitVAArgInst(VAArgInst &I) {
IMPLEMENT_VAARG(Double);
default:
cerr << "Unhandled dest type for vaarg instruction: " << *Ty << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
// Set the Value of this Instruction.
@ -1263,7 +1263,7 @@ GenericValue Interpreter::getConstantExprValue (ConstantExpr *CE,
break;
default:
cerr << "Unhandled ConstantExpr: " << *CE << "\n";
llvm_unreachable();
llvm_unreachable(0);
return GenericValue();
}
return Dest;
@ -1345,7 +1345,7 @@ void Interpreter::run() {
DOUT << " --> ";
const GenericValue &Val = SF.Values[&I];
switch (I.getType()->getTypeID()) {
default: LLVM_UNREACHABLE("Invalid GenericValue Type");
default: llvm_unreachable("Invalid GenericValue Type");
case Type::VoidTyID: DOUT << "void"; break;
case Type::FloatTyID: DOUT << "float " << Val.FloatVal; break;
case Type::DoubleTyID: DOUT << "double " << Val.DoubleVal; break;

4
lib/ExecutionEngine/Interpreter/Interpreter.h
View File

@ -147,7 +147,7 @@ public:
void visitStoreInst(StoreInst &I);
void visitGetElementPtrInst(GetElementPtrInst &I);
void visitPHINode(PHINode &PN) {
LLVM_UNREACHABLE("PHI nodes already handled!");
llvm_unreachable("PHI nodes already handled!");
}
void visitTruncInst(TruncInst &I);
void visitZExtInst(ZExtInst &I);
@ -177,7 +177,7 @@ public:
void visitVAArgInst(VAArgInst &I);
void visitInstruction(Instruction &I) {
cerr << I;
LLVM_UNREACHABLE("Instruction not interpretable yet!");
llvm_unreachable("Instruction not interpretable yet!");
}
GenericValue callExternalFunction(Function *F,

8
lib/ExecutionEngine/JIT/JIT.cpp
View File

@ -410,7 +410,7 @@ GenericValue JIT::runFunction(Function *F,
if (ArgValues.empty()) {
GenericValue rv;
switch (RetTy->getTypeID()) {
default: LLVM_UNREACHABLE("Unknown return type for function call!");
default: llvm_unreachable("Unknown return type for function call!");
case Type::IntegerTyID: {
unsigned BitWidth = cast<IntegerType>(RetTy)->getBitWidth();
if (BitWidth == 1)
@ -424,7 +424,7 @@ GenericValue JIT::runFunction(Function *F,
else if (BitWidth <= 64)
rv.IntVal = APInt(BitWidth, ((int64_t(*)())(intptr_t)FPtr)());
else
LLVM_UNREACHABLE("Integer types > 64 bits not supported");
llvm_unreachable("Integer types > 64 bits not supported");
return rv;
}
case Type::VoidTyID:
@ -439,7 +439,7 @@ GenericValue JIT::runFunction(Function *F,
case Type::X86_FP80TyID:
case Type::FP128TyID:
case Type::PPC_FP128TyID:
LLVM_UNREACHABLE("long double not supported yet");
llvm_unreachable("long double not supported yet");
return rv;
case Type::PointerTyID:
return PTOGV(((void*(*)())(intptr_t)FPtr)());
@ -467,7 +467,7 @@ GenericValue JIT::runFunction(Function *F,
const Type *ArgTy = FTy->getParamType(i);
const GenericValue &AV = ArgValues[i];
switch (ArgTy->getTypeID()) {
default: LLVM_UNREACHABLE("Unknown argument type for function call!");
default: llvm_unreachable("Unknown argument type for function call!");
case Type::IntegerTyID:
C = ConstantInt::get(AV.IntVal);
break;

8
lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp
View File

@ -111,7 +111,7 @@ JITDwarfEmitter::EmitFrameMoves(intptr_t BaseLabelPtr,
JCE->emitULEB128Bytes(Offset);
} else {
LLVM_UNREACHABLE("Machine move no supported yet.");
llvm_unreachable("Machine move no supported yet.");
}
} else if (Src.isReg() &&
Src.getReg() == MachineLocation::VirtualFP) {
@ -119,7 +119,7 @@ JITDwarfEmitter::EmitFrameMoves(intptr_t BaseLabelPtr,
JCE->emitByte(dwarf::DW_CFA_def_cfa_register);
JCE->emitULEB128Bytes(RI->getDwarfRegNum(Dst.getReg(), true));
} else {
LLVM_UNREACHABLE("Machine move no supported yet.");
llvm_unreachable("Machine move no supported yet.");
}
} else {
unsigned Reg = RI->getDwarfRegNum(Src.getReg(), true);
@ -762,7 +762,7 @@ JITDwarfEmitter::GetFrameMovesSizeInBytes(intptr_t BaseLabelPtr,
FinalSize += TargetAsmInfo::getULEB128Size(Offset);
} else {
LLVM_UNREACHABLE("Machine move no supported yet.");
llvm_unreachable("Machine move no supported yet.");
}
} else if (Src.isReg() &&
Src.getReg() == MachineLocation::VirtualFP) {
@ -771,7 +771,7 @@ JITDwarfEmitter::GetFrameMovesSizeInBytes(intptr_t BaseLabelPtr,
unsigned RegNum = RI->getDwarfRegNum(Dst.getReg(), true);
FinalSize += TargetAsmInfo::getULEB128Size(RegNum);
} else {
LLVM_UNREACHABLE("Machine move no supported yet.");
llvm_unreachable("Machine move no supported yet.");
}
} else {
unsigned Reg = RI->getDwarfRegNum(Src.getReg(), true);

4
lib/Linker/LinkItems.cpp
View File

@ -81,7 +81,7 @@ bool Linker::LinkInLibrary(const std::string& Lib, bool& is_native) {
std::string Magic;
Pathname.getMagicNumber(Magic, 64);
switch (sys::IdentifyFileType(Magic.c_str(), 64)) {
default: LLVM_UNREACHABLE("Bad file type identification");
default: llvm_unreachable("Bad file type identification");
case sys::Unknown_FileType:
return warning("Supposed library '" + Lib + "' isn't a library.");
@ -179,7 +179,7 @@ bool Linker::LinkInFile(const sys::Path &File, bool &is_native) {
std::string Magic;
File.getMagicNumber(Magic, 64);
switch (sys::IdentifyFileType(Magic.c_str(), 64)) {
default: LLVM_UNREACHABLE("Bad file type identification");
default: llvm_unreachable("Bad file type identification");
case sys::Unknown_FileType:
return warning("Ignoring file '" + File.toString() +
"' because does not contain bitcode.");

8
lib/Linker/LinkModules.cpp
View File

@ -393,7 +393,7 @@ static Value *RemapOperand(const Value *In,
Result = CE->getWithOperands(Ops);
} else {
assert(!isa<GlobalValue>(CPV) && "Unmapped global?");
LLVM_UNREACHABLE("Unknown type of derived type constant value!");
llvm_unreachable("Unknown type of derived type constant value!");
}
} else if (isa<InlineAsm>(In)) {
Result = const_cast<Value*>(In);
@ -410,7 +410,7 @@ static Value *RemapOperand(const Value *In,
PrintMap(ValueMap);
cerr << "Couldn't remap value: " << (void*)In << " " << *In << "\n";
LLVM_UNREACHABLE("Couldn't remap value!");
llvm_unreachable("Couldn't remap value!");
#endif
return 0;
}
@ -900,9 +900,9 @@ static bool LinkGlobalInits(Module *Dest, const Module *Src,
// Nothing is required, mapped values will take the new global
// automatically.
} else if (DGVar->hasAppendingLinkage()) {
LLVM_UNREACHABLE("Appending linkage unimplemented!");
llvm_unreachable("Appending linkage unimplemented!");
} else {
LLVM_UNREACHABLE("Unknown linkage!");
llvm_unreachable("Unknown linkage!");
}
} else {
// Copy the initializer over now...

6
lib/MC/MCAsmStreamer.cpp
View File

@ -204,7 +204,7 @@ void MCAsmStreamer::EmitValue(const MCValue &Value, unsigned Size) {
// Need target hooks to know how to print this.
switch (Size) {
default:
LLVM_UNREACHABLE("Invalid size for machine code value!");
llvm_unreachable("Invalid size for machine code value!");
case 1: OS << ".byte"; break;
case 2: OS << ".short"; break;
case 4: OS << ".long"; break;
@ -225,9 +225,9 @@ void MCAsmStreamer::EmitValueToAlignment(unsigned ByteAlignment, int64_t Value,
switch (ValueSize) {
default:
LLVM_UNREACHABLE("Invalid size for machine code value!");
llvm_unreachable("Invalid size for machine code value!");
case 8:
LLVM_UNREACHABLE("Unsupported alignment size!");
llvm_unreachable("Unsupported alignment size!");
case 1: OS << (IsPow2 ? ".p2align" : ".balign"); break;
case 2: OS << (IsPow2 ? ".p2alignw" : ".balignw"); break;
case 4: OS << (IsPow2 ? ".p2alignl" : ".balignl"); break;

14
lib/Support/APFloat.cpp
View File

@ -1069,7 +1069,7 @@ APFloat::roundAwayFromZero(roundingMode rounding_mode,
switch (rounding_mode) {
default:
llvm_unreachable();
llvm_unreachable(0);
case rmNearestTiesToAway:
return lost_fraction == lfExactlyHalf || lost_fraction == lfMoreThanHalf;
@ -1208,7 +1208,7 @@ APFloat::addOrSubtractSpecials(const APFloat &rhs, bool subtract)
{
switch (convolve(category, rhs.category)) {
default:
llvm_unreachable();
llvm_unreachable(0);
case convolve(fcNaN, fcZero):
case convolve(fcNaN, fcNormal):
@ -1332,7 +1332,7 @@ APFloat::multiplySpecials(const APFloat &rhs)
{
switch (convolve(category, rhs.category)) {
default:
llvm_unreachable();
llvm_unreachable(0);
case convolve(fcNaN, fcZero):
case convolve(fcNaN, fcNormal):
@ -1374,7 +1374,7 @@ APFloat::divideSpecials(const APFloat &rhs)
{
switch (convolve(category, rhs.category)) {
default:
llvm_unreachable();
llvm_unreachable(0);
case convolve(fcNaN, fcZero):
case convolve(fcNaN, fcNormal):
@ -1416,7 +1416,7 @@ APFloat::modSpecials(const APFloat &rhs)
{
switch (convolve(category, rhs.category)) {
default:
llvm_unreachable();
llvm_unreachable(0);
case convolve(fcNaN, fcZero):
case convolve(fcNaN, fcNormal):
@ -1693,7 +1693,7 @@ APFloat::compare(const APFloat &rhs) const
switch (convolve(category, rhs.category)) {
default:
llvm_unreachable();
llvm_unreachable(0);
case convolve(fcNaN, fcZero):
case convolve(fcNaN, fcNormal):
@ -2930,7 +2930,7 @@ APFloat::initFromAPInt(const APInt& api, bool isIEEE)
else if (api.getBitWidth()==128 && !isIEEE)
return initFromPPCDoubleDoubleAPInt(api);
else
llvm_unreachable();
llvm_unreachable(0);
}
APFloat::APFloat(const APInt& api, bool isIEEE)

8
lib/Support/APInt.cpp
View File

@ -1387,7 +1387,7 @@ APInt APInt::sqrt() const {
else
return x_old + 1;
} else
LLVM_UNREACHABLE("Error in APInt::sqrt computation");
llvm_unreachable("Error in APInt::sqrt computation");
return x_old + 1;
}
@ -2033,7 +2033,7 @@ void APInt::fromString(unsigned numbits, const char *str, unsigned slen,
char cdigit = str[i];
if (radix == 16) {
if (!isxdigit(cdigit))
LLVM_UNREACHABLE("Invalid hex digit in string");
llvm_unreachable("Invalid hex digit in string");
if (isdigit(cdigit))
digit = cdigit - '0';
else if (cdigit >= 'a')
@ -2041,7 +2041,7 @@ void APInt::fromString(unsigned numbits, const char *str, unsigned slen,
else if (cdigit >= 'A')
digit = cdigit - 'A' + 10;
else
LLVM_UNREACHABLE("huh? we shouldn't get here");
llvm_unreachable("huh? we shouldn't get here");
} else if (isdigit(cdigit)) {
digit = cdigit - '0';
assert((radix == 10 ||
@ -2049,7 +2049,7 @@ void APInt::fromString(unsigned numbits, const char *str, unsigned slen,
(radix == 2 && (digit == 0 || digit == 1))) &&
"Invalid digit in string for given radix");
} else {
LLVM_UNREACHABLE("Invalid character in digit string");
llvm_unreachable("Invalid character in digit string");
}
// Shift or multiply the value by the radix

4
lib/Support/CommandLine.cpp
View File

@ -205,7 +205,7 @@ static inline bool ProvideOption(Option *Handler, const char *ArgName,
cerr << ProgramName
<< ": Bad ValueMask flag! CommandLine usage error:"
<< Handler->getValueExpectedFlag() << "\n";
llvm_unreachable();
llvm_unreachable(0);
}
// If this isn't a multi-arg option, just run the handler.
@ -693,7 +693,7 @@ void cl::ParseCommandLineOptions(int argc, char **argv,
ValNo++;
break;
default:
LLVM_UNREACHABLE("Internal error, unexpected NumOccurrences flag in "
llvm_unreachable("Internal error, unexpected NumOccurrences flag in "
"positional argument processing!");
}
}

42
lib/Support/Dwarf.cpp
View File

@ -84,7 +84,7 @@ const char *TagString(unsigned Tag) {
case DW_TAG_lo_user: return "DW_TAG_lo_user";
case DW_TAG_hi_user: return "DW_TAG_hi_user";
}
LLVM_UNREACHABLE("Unknown Dwarf Tag");
llvm_unreachable("Unknown Dwarf Tag");
return "";
}
@ -95,7 +95,7 @@ const char *ChildrenString(unsigned Children) {
case DW_CHILDREN_no: return "CHILDREN_no";
case DW_CHILDREN_yes: return "CHILDREN_yes";
}
LLVM_UNREACHABLE("Unknown Dwarf ChildrenFlag");
llvm_unreachable("Unknown Dwarf ChildrenFlag");
return "";
}
@ -206,7 +206,7 @@ const char *AttributeString(unsigned Attribute) {
case DW_AT_APPLE_major_runtime_vers: return "DW_AT_APPLE_major_runtime_vers";
case DW_AT_APPLE_runtime_class: return "DW_AT_APPLE_runtime_class";
}
LLVM_UNREACHABLE("Unknown Dwarf Attribute");
llvm_unreachable("Unknown Dwarf Attribute");
return "";
}
@ -236,7 +236,7 @@ const char *FormEncodingString(unsigned Encoding) {
case DW_FORM_ref_udata: return "FORM_ref_udata";
case DW_FORM_indirect: return "FORM_indirect";
}
LLVM_UNREACHABLE("Unknown Dwarf Form Encoding");
llvm_unreachable("Unknown Dwarf Form Encoding");
return "";
}
@ -311,7 +311,7 @@ const char *OperationEncodingString(unsigned Encoding) {
case DW_OP_lo_user: return "OP_lo_user";
case DW_OP_hi_user: return "OP_hi_user";
}
LLVM_UNREACHABLE("Unknown Dwarf Operation Encoding");
llvm_unreachable("Unknown Dwarf Operation Encoding");
return "";
}
@ -337,7 +337,7 @@ const char *AttributeEncodingString(unsigned Encoding) {
case DW_ATE_lo_user: return "ATE_lo_user";
case DW_ATE_hi_user: return "ATE_hi_user";
}
LLVM_UNREACHABLE("Unknown Dwarf Attribute Encoding");
llvm_unreachable("Unknown Dwarf Attribute Encoding");
return "";
}
@ -351,7 +351,7 @@ const char *DecimalSignString(unsigned Sign) {
case DW_DS_leading_separate: return "DS_leading_separate";
case DW_DS_trailing_separate: return "DS_trailing_separate";
}
LLVM_UNREACHABLE("Unknown Dwarf Decimal Sign Attribute");
llvm_unreachable("Unknown Dwarf Decimal Sign Attribute");
return "";
}
@ -365,7 +365,7 @@ const char *EndianityString(unsigned Endian) {
case DW_END_lo_user: return "END_lo_user";
case DW_END_hi_user: return "END_hi_user";
}
LLVM_UNREACHABLE("Unknown Dwarf Endianity");
llvm_unreachable("Unknown Dwarf Endianity");
return "";
}
@ -378,7 +378,7 @@ const char *AccessibilityString(unsigned Access) {
case DW_ACCESS_protected: return "ACCESS_protected";
case DW_ACCESS_private: return "ACCESS_private";
}
LLVM_UNREACHABLE("Unknown Dwarf Accessibility");
llvm_unreachable("Unknown Dwarf Accessibility");
return "";
}
@ -390,7 +390,7 @@ const char *VisibilityString(unsigned Visibility) {
case DW_VIS_exported: return "VIS_exported";
case DW_VIS_qualified: return "VIS_qualified";
}
LLVM_UNREACHABLE("Unknown Dwarf Visibility");
llvm_unreachable("Unknown Dwarf Visibility");
return "";
}
@ -402,7 +402,7 @@ const char *VirtualityString(unsigned Virtuality) {
case DW_VIRTUALITY_virtual: return "VIRTUALITY_virtual";
case DW_VIRTUALITY_pure_virtual: return "VIRTUALITY_pure_virtual";
}
LLVM_UNREACHABLE("Unknown Dwarf Virtuality");
llvm_unreachable("Unknown Dwarf Virtuality");
return "";
}
@ -432,7 +432,7 @@ const char *LanguageString(unsigned Language) {
case DW_LANG_lo_user: return "LANG_lo_user";
case DW_LANG_hi_user: return "LANG_hi_user";
}
LLVM_UNREACHABLE("Unknown Dwarf Language");
llvm_unreachable("Unknown Dwarf Language");
return "";
}
@ -445,7 +445,7 @@ const char *CaseString(unsigned Case) {
case DW_ID_down_case: return "ID_down_case";
case DW_ID_case_insensitive: return "ID_case_insensitive";
}
LLVM_UNREACHABLE("Unknown Dwarf Identifier Case");
llvm_unreachable("Unknown Dwarf Identifier Case");
return "";
}
@ -459,7 +459,7 @@ const char *ConventionString(unsigned Convention) {
case DW_CC_lo_user: return "CC_lo_user";
case DW_CC_hi_user: return "CC_hi_user";
}
LLVM_UNREACHABLE("Unknown Dwarf Calling Convention");
llvm_unreachable("Unknown Dwarf Calling Convention");
return "";
}
@ -472,7 +472,7 @@ const char *InlineCodeString(unsigned Code) {
case DW_INL_declared_not_inlined: return "INL_declared_not_inlined";
case DW_INL_declared_inlined: return "INL_declared_inlined";
}
LLVM_UNREACHABLE("Unknown Dwarf Inline Code");
llvm_unreachable("Unknown Dwarf Inline Code");
return "";
}
@ -483,7 +483,7 @@ const char *ArrayOrderString(unsigned Order) {
case DW_ORD_row_major: return "ORD_row_major";
case DW_ORD_col_major: return "ORD_col_major";
}
LLVM_UNREACHABLE("Unknown Dwarf Array Order");
llvm_unreachable("Unknown Dwarf Array Order");
return "";
}
@ -494,7 +494,7 @@ const char *DiscriminantString(unsigned Discriminant) {
case DW_DSC_label: return "DSC_label";
case DW_DSC_range: return "DSC_range";
}
LLVM_UNREACHABLE("Unknown Dwarf Discriminant Descriptor");
llvm_unreachable("Unknown Dwarf Discriminant Descriptor");
return "";
}
@ -515,7 +515,7 @@ const char *LNStandardString(unsigned Standard) {
case DW_LNS_set_epilogue_begin: return "LNS_set_epilogue_begin";
case DW_LNS_set_isa: return "LNS_set_isa";
}
LLVM_UNREACHABLE("Unknown Dwarf Line Number Standard");
llvm_unreachable("Unknown Dwarf Line Number Standard");
return "";
}
@ -530,7 +530,7 @@ const char *LNExtendedString(unsigned Encoding) {
case DW_LNE_lo_user: return "LNE_lo_user";
case DW_LNE_hi_user: return "LNE_hi_user";
}
LLVM_UNREACHABLE("Unknown Dwarf Line Number Extended Opcode Encoding");
llvm_unreachable("Unknown Dwarf Line Number Extended Opcode Encoding");
return "";
}
@ -545,7 +545,7 @@ const char *MacinfoString(unsigned Encoding) {
case DW_MACINFO_end_file: return "MACINFO_end_file";
case DW_MACINFO_vendor_ext: return "MACINFO_vendor_ext";
}
LLVM_UNREACHABLE("Unknown Dwarf Macinfo Type Encodings");
llvm_unreachable("Unknown Dwarf Macinfo Type Encodings");
return "";
}
@ -581,7 +581,7 @@ const char *CallFrameString(unsigned Encoding) {
case DW_CFA_lo_user: return "CFA_lo_user";
case DW_CFA_hi_user: return "CFA_hi_user";
}
LLVM_UNREACHABLE("Unknown Dwarf Call Frame Instruction Encodings");
llvm_unreachable("Unknown Dwarf Call Frame Instruction Encodings");
return "";
}

2
lib/Support/ErrorHandling.cpp
View File

@ -44,7 +44,7 @@ void llvm_report_error(const std::string &reason) {
exit(1);
}
void llvm_unreachable(const char *msg, const char *file, unsigned line) {
void llvm_unreachable_internal(const char *msg, const char *file, unsigned line) {
if (msg)
errs() << msg << "\n";
errs() << "UNREACHABLE executed";

2
lib/Support/FoldingSet.cpp
View File

@ -51,7 +51,7 @@ void FoldingSetNodeID::AddInteger(unsigned long I) {
else if (sizeof(long) == sizeof(long long)) {
AddInteger((unsigned long long)I);
} else {
LLVM_UNREACHABLE("unexpected sizeof(long)");
llvm_unreachable("unexpected sizeof(long)");
}
}
void FoldingSetNodeID::AddInteger(long long I) {

4
lib/Target/ARM/ARM.h
View File

@ -52,7 +52,7 @@ namespace ARMCC {
inline static CondCodes getOppositeCondition(CondCodes CC){
switch (CC) {
default: LLVM_UNREACHABLE("Unknown condition code");
default: llvm_unreachable("Unknown condition code");
case EQ: return NE;
case NE: return EQ;
case HS: return LO;
@ -73,7 +73,7 @@ namespace ARMCC {
inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
switch (CC) {
default: LLVM_UNREACHABLE("Unknown condition code");
default: llvm_unreachable("Unknown condition code");
case ARMCC::EQ: return "eq";
case ARMCC::NE: return "ne";
case ARMCC::HS: return "hs";

6
lib/Target/ARM/ARMAddressingModes.h
View File

@ -38,7 +38,7 @@ namespace ARM_AM {
static inline const char *getShiftOpcStr(ShiftOpc Op) {
switch (Op) {
default: LLVM_UNREACHABLE("Unknown shift opc!");
default: llvm_unreachable("Unknown shift opc!");
case ARM_AM::asr: return "asr";
case ARM_AM::lsl: return "lsl";
case ARM_AM::lsr: return "lsr";
@ -71,7 +71,7 @@ namespace ARM_AM {
static inline const char *getAMSubModeStr(AMSubMode Mode) {
switch (Mode) {
default: LLVM_UNREACHABLE("Unknown addressing sub-mode!");
default: llvm_unreachable("Unknown addressing sub-mode!");
case ARM_AM::ia: return "ia";
case ARM_AM::ib: return "ib";
case ARM_AM::da: return "da";
@ -81,7 +81,7 @@ namespace ARM_AM {
static inline const char *getAMSubModeAltStr(AMSubMode Mode, bool isLD) {
switch (Mode) {
default: LLVM_UNREACHABLE("Unknown addressing sub-mode!");
default: llvm_unreachable("Unknown addressing sub-mode!");
case ARM_AM::ia: return isLD ? "fd" : "ea";
case ARM_AM::ib: return isLD ? "ed" : "fa";
case ARM_AM::da: return isLD ? "fa" : "ed";

2
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -434,7 +434,7 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
return 0;
switch (MI->getOpcode()) {
default:
LLVM_UNREACHABLE("Unknown or unset size field for instr!");
llvm_unreachable("Unknown or unset size field for instr!");
case TargetInstrInfo::IMPLICIT_DEF:
case TargetInstrInfo::DECLARE:
case TargetInstrInfo::DBG_LABEL:

10
lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@ -72,7 +72,7 @@ unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
case S30: return 30;
case S31: return 31;
default:
LLVM_UNREACHABLE("Unknown ARM register!");
llvm_unreachable("Unknown ARM register!");
}
}
@ -83,7 +83,7 @@ unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
using namespace ARM;
switch (RegEnum) {
default:
LLVM_UNREACHABLE("Unknown ARM register!");
llvm_unreachable("Unknown ARM register!");
case R0: case D0: return 0;
case R1: case D1: return 1;
case R2: case D2: return 2;
@ -707,12 +707,12 @@ unsigned ARMBaseRegisterInfo::getFrameRegister(MachineFunction &MF) const {
}
unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
LLVM_UNREACHABLE("What is the exception register");
llvm_unreachable("What is the exception register");
return 0;
}
unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
LLVM_UNREACHABLE("What is the exception handler register");
llvm_unreachable("What is the exception handler register");
return 0;
}
@ -1138,7 +1138,7 @@ eliminateFrameIndex(MachineBasicBlock::iterator II,
break;
}
default:
LLVM_UNREACHABLE("Unsupported addressing mode!");
llvm_unreachable("Unsupported addressing mode!");
break;
}

20
lib/Target/ARM/ARMCodeEmitter.cpp
View File

@ -223,7 +223,7 @@ bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
template<class CodeEmitter>
unsigned Emitter<CodeEmitter>::getShiftOp(unsigned Imm) const {
switch (ARM_AM::getAM2ShiftOpc(Imm)) {
default: LLVM_UNREACHABLE("Unknown shift opc!");
default: llvm_unreachable("Unknown shift opc!");
case ARM_AM::asr: return 2;
case ARM_AM::lsl: return 0;
case ARM_AM::lsr: return 1;
@ -260,7 +260,7 @@ unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI,
#ifndef NDEBUG
cerr << MO;
#endif
llvm_unreachable();
llvm_unreachable(0);
}
return 0;
}
@ -340,7 +340,7 @@ void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI) {
NumEmitted++; // Keep track of the # of mi's emitted
switch (MI.getDesc().TSFlags & ARMII::FormMask) {
default: {
LLVM_UNREACHABLE("Unhandled instruction encoding format!");
llvm_unreachable("Unhandled instruction encoding format!");
break;
}
case ARMII::Pseudo:
@ -458,10 +458,10 @@ void Emitter<CodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) {
else if (CFP->getType() == Type::DoubleTy)
emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
else {
LLVM_UNREACHABLE("Unable to handle this constantpool entry!");
llvm_unreachable("Unable to handle this constantpool entry!");
}
} else {
LLVM_UNREACHABLE("Unable to handle this constantpool entry!");
llvm_unreachable("Unable to handle this constantpool entry!");
}
}
}
@ -589,7 +589,7 @@ void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
unsigned Opcode = MI.getDesc().Opcode;
switch (Opcode) {
default:
LLVM_UNREACHABLE("ARMCodeEmitter::emitPseudoInstruction");//FIXME:
llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");//FIXME:
case TargetInstrInfo::INLINEASM: {
// We allow inline assembler nodes with empty bodies - they can
// implicitly define registers, which is ok for JIT.
@ -676,7 +676,7 @@ unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue(
// ROR - 0111
// RRX - 0110 and bit[11:8] clear.
switch (SOpc) {
default: LLVM_UNREACHABLE("Unknown shift opc!");
default: llvm_unreachable("Unknown shift opc!");
case ARM_AM::lsl: SBits = 0x1; break;
case ARM_AM::lsr: SBits = 0x3; break;
case ARM_AM::asr: SBits = 0x5; break;
@ -690,7 +690,7 @@ unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue(
// ASR - 100
// ROR - 110
switch (SOpc) {
default: LLVM_UNREACHABLE("Unknown shift opc!");
default: llvm_unreachable("Unknown shift opc!");
case ARM_AM::lsl: SBits = 0x0; break;
case ARM_AM::lsr: SBits = 0x2; break;
case ARM_AM::asr: SBits = 0x4; break;
@ -959,7 +959,7 @@ static unsigned getAddrModeUPBits(unsigned Mode) {
// DA - Decrement after - bit U = 0 and bit P = 0
// DB - Decrement before - bit U = 0 and bit P = 1
switch (Mode) {
default: LLVM_UNREACHABLE("Unknown addressing sub-mode!");
default: llvm_unreachable("Unknown addressing sub-mode!");
case ARM_AM::da: break;
case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
@ -1123,7 +1123,7 @@ void Emitter<CodeEmitter>::emitBranchInstruction(const MachineInstr &MI) {
const TargetInstrDesc &TID = MI.getDesc();
if (TID.Opcode == ARM::TPsoft) {
LLVM_UNREACHABLE("ARM::TPsoft FIXME"); // FIXME
llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
}
// Part of binary is determined by TableGn.

2
lib/Target/ARM/ARMConstantIslandPass.cpp
View File

@ -449,7 +449,7 @@ void ARMConstantIslands::InitialFunctionScan(MachineFunction &Fn,
Bits = 8; // Taking the address of a CP entry.
break;
}
LLVM_UNREACHABLE("Unknown addressing mode for CP reference!");
llvm_unreachable("Unknown addressing mode for CP reference!");
case ARMII::AddrMode1: // AM1: 8 bits << 2
Bits = 8;
Scale = 4; // Taking the address of a CP entry.

42
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -470,7 +470,7 @@ unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
switch (CC) {
default: LLVM_UNREACHABLE("Unknown condition code!");
default: llvm_unreachable("Unknown condition code!");
case ISD::SETNE: return ARMCC::NE;
case ISD::SETEQ: return ARMCC::EQ;
case ISD::SETGT: return ARMCC::GT;
@ -492,7 +492,7 @@ static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
bool Invert = false;
CondCode2 = ARMCC::AL;
switch (CC) {
default: LLVM_UNREACHABLE("Unknown FP condition!");
default: llvm_unreachable("Unknown FP condition!");
case ISD::SETEQ:
case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
case ISD::SETGT:
@ -661,7 +661,7 @@ CCAssignFn *ARMTargetLowering::CCAssignFnForNode(unsigned CC,
bool Return) const {
switch (CC) {
default:
LLVM_UNREACHABLE("Unsupported calling convention");
llvm_unreachable("Unsupported calling convention");
case CallingConv::C:
case CallingConv::Fast:
// Use target triple & subtarget features to do actual dispatch.
@ -745,7 +745,7 @@ LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
}
switch (VA.getLocInfo()) {
default: LLVM_UNREACHABLE("Unknown loc info!");
default: llvm_unreachable("Unknown loc info!");
case CCValAssign::Full: break;
case CCValAssign::BCvt:
Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
@ -858,7 +858,7 @@ SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
// Promote the value if needed.
switch (VA.getLocInfo()) {
default: LLVM_UNREACHABLE("Unknown loc info!");
default: llvm_unreachable("Unknown loc info!");
case CCValAssign::Full: break;
case CCValAssign::SExt:
Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
@ -1060,7 +1060,7 @@ SDValue ARMTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
SDValue Arg = Op.getOperand(realRVLocIdx*2+1);
switch (VA.getLocInfo()) {
default: LLVM_UNREACHABLE("Unknown loc info!");
default: llvm_unreachable("Unknown loc info!");
case CCValAssign::Full: break;
case CCValAssign::BCvt:
Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
@ -1442,7 +1442,7 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
// to 32 bits. Insert an assert[sz]ext to capture this, then
// truncate to the right size.
switch (VA.getLocInfo()) {
default: LLVM_UNREACHABLE("Unknown loc info!");
default: llvm_unreachable("Unknown loc info!");
case CCValAssign::Full: break;
case CCValAssign::BCvt:
ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
@ -2006,7 +2006,7 @@ static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
if (Op.getOperand(1).getValueType().isFloatingPoint()) {
switch (SetCCOpcode) {
default: LLVM_UNREACHABLE("Illegal FP comparison"); break;
default: llvm_unreachable("Illegal FP comparison"); break;
case ISD::SETUNE:
case ISD::SETNE: Invert = true; // Fallthrough
case ISD::SETOEQ:
@ -2045,7 +2045,7 @@ static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
} else {
// Integer comparisons.
switch (SetCCOpcode) {
default: LLVM_UNREACHABLE("Illegal integer comparison"); break;
default: llvm_unreachable("Illegal integer comparison"); break;
case ISD::SETNE: Invert = true;
case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
case ISD::SETLT: Swap = true;
@ -2149,7 +2149,7 @@ static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef,
}
default:
LLVM_UNREACHABLE("unexpected size for isVMOVSplat");
llvm_unreachable("unexpected size for isVMOVSplat");
break;
}
@ -2191,7 +2191,7 @@ static SDValue BuildSplat(SDValue Val, MVT VT, SelectionDAG &DAG, DebugLoc dl) {
case 16: CanonicalVT = MVT::v4i16; break;
case 32: CanonicalVT = MVT::v2i32; break;
case 64: CanonicalVT = MVT::v1i64; break;
default: LLVM_UNREACHABLE("unexpected splat element type"); break;
default: llvm_unreachable("unexpected splat element type"); break;
}
} else {
assert(VT.is128BitVector() && "unknown splat vector size");
@ -2200,7 +2200,7 @@ static SDValue BuildSplat(SDValue Val, MVT VT, SelectionDAG &DAG, DebugLoc dl) {
case 16: CanonicalVT = MVT::v8i16; break;
case 32: CanonicalVT = MVT::v4i32; break;
case 64: CanonicalVT = MVT::v2i64; break;
default: LLVM_UNREACHABLE("unexpected splat element type"); break;
default: llvm_unreachable("unexpected splat element type"); break;
}
}
@ -2260,7 +2260,7 @@ static SDValue LowerCONCAT_VECTORS(SDValue Op) {
SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
default: LLVM_UNREACHABLE("Don't know how to custom lower this!");
default: llvm_unreachable("Don't know how to custom lower this!");
case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
case ISD::GlobalAddress:
return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
@ -2303,7 +2303,7 @@ void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
SelectionDAG &DAG) {
switch (N->getOpcode()) {
default:
LLVM_UNREACHABLE("Don't know how to custom expand this!");
llvm_unreachable("Don't know how to custom expand this!");
return;
case ISD::BIT_CONVERT:
Results.push_back(ExpandBIT_CONVERT(N, DAG));
@ -2595,7 +2595,7 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
case Intrinsic::arm_neon_vshiftlu:
if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
break;
LLVM_UNREACHABLE("invalid shift count for vshll intrinsic");
llvm_unreachable("invalid shift count for vshll intrinsic");
case Intrinsic::arm_neon_vrshifts:
case Intrinsic::arm_neon_vrshiftu:
@ -2612,7 +2612,7 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
case Intrinsic::arm_neon_vqshiftsu:
if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
break;
LLVM_UNREACHABLE("invalid shift count for vqshlu intrinsic");
llvm_unreachable("invalid shift count for vqshlu intrinsic");
case Intrinsic::arm_neon_vshiftn:
case Intrinsic::arm_neon_vrshiftn:
@ -2625,10 +2625,10 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
// Narrowing shifts require an immediate right shift.
if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
break;
LLVM_UNREACHABLE("invalid shift count for narrowing vector shift intrinsic");
llvm_unreachable("invalid shift count for narrowing vector shift intrinsic");
default:
LLVM_UNREACHABLE("unhandled vector shift");
llvm_unreachable("unhandled vector shift");
}
switch (IntNo) {
@ -2686,7 +2686,7 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
VShiftOpc = ARMISD::VSRI;
else {
LLVM_UNREACHABLE("invalid shift count for vsli/vsri intrinsic");
llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
}
return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
@ -2720,7 +2720,7 @@ static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
int64_t Cnt;
switch (N->getOpcode()) {
default: LLVM_UNREACHABLE("unexpected shift opcode");
default: llvm_unreachable("unexpected shift opcode");
case ISD::SHL:
if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
@ -2763,7 +2763,7 @@ static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
unsigned Opc = 0;
switch (N->getOpcode()) {
default: LLVM_UNREACHABLE("unexpected opcode");
default: llvm_unreachable("unexpected opcode");
case ISD::SIGN_EXTEND:
Opc = ARMISD::VGETLANEs;
break;

6
lib/Target/ARM/ARMJITInfo.cpp
View File

@ -104,7 +104,7 @@ extern "C" {
);
#else // Not an ARM host
void ARMCompilationCallback() {
LLVM_UNREACHABLE("Cannot call ARMCompilationCallback() on a non-ARM arch!");
llvm_unreachable("Cannot call ARMCompilationCallback() on a non-ARM arch!");
}
#endif
}
@ -123,12 +123,12 @@ extern "C" void ARMCompilationCallbackC(intptr_t StubAddr) {
// ldr pc, [pc,#-4]
// <addr>
if (!sys::Memory::setRangeWritable((void*)StubAddr, 8)) {
LLVM_UNREACHABLE("ERROR: Unable to mark stub writable");
llvm_unreachable("ERROR: Unable to mark stub writable");
}
*(intptr_t *)StubAddr = 0xe51ff004; // ldr pc, [pc, #-4]
*(intptr_t *)(StubAddr+4) = NewVal;
if (!sys::Memory::setRangeExecutable((void*)StubAddr, 8)) {
LLVM_UNREACHABLE("ERROR: Unable to mark stub executable");
llvm_unreachable("ERROR: Unable to mark stub executable");
}
}

6
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@ -138,7 +138,7 @@ static int getLoadStoreMultipleOpcode(int Opcode) {
case ARM::FSTD:
NumFSTMGened++;
return ARM::FSTMD;
default: LLVM_UNREACHABLE("Unhandled opcode!");
default: llvm_unreachable("Unhandled opcode!");
}
return 0;
}
@ -513,7 +513,7 @@ static unsigned getPreIndexedLoadStoreOpcode(unsigned Opc) {
case ARM::t2STRi8:
case ARM::t2STRi12:
return ARM::t2STR_PRE;
default: LLVM_UNREACHABLE("Unhandled opcode!");
default: llvm_unreachable("Unhandled opcode!");
}
return 0;
}
@ -532,7 +532,7 @@ static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc) {
case ARM::t2STRi8:
case ARM::t2STRi12:
return ARM::t2STR_POST;
default: LLVM_UNREACHABLE("Unhandled opcode!");
default: llvm_unreachable("Unhandled opcode!");
}
return 0;
}

6
lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
View File

@ -211,7 +211,7 @@ bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
// Print out labels for the function.
const Function *F = MF.getFunction();
switch (F->getLinkage()) {
default: LLVM_UNREACHABLE("Unknown linkage type!");
default: llvm_unreachable("Unknown linkage type!");
case Function::PrivateLinkage:
case Function::InternalLinkage:
SwitchToTextSection("\t.text", F);
@ -308,7 +308,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
O << TRI->getAsmName(Reg);
}
} else
LLVM_UNREACHABLE("not implemented");
llvm_unreachable("not implemented");
break;
}
case MachineOperand::MO_Immediate: {
@ -1139,7 +1139,7 @@ void ARMAsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) {
case GlobalValue::InternalLinkage:
break;
default:
LLVM_UNREACHABLE("Unknown linkage type!");
llvm_unreachable("Unknown linkage type!");
}
EmitAlignment(Align, GVar);

2
lib/Target/ARM/Thumb1RegisterInfo.cpp
View File

@ -511,7 +511,7 @@ void Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
break;
}
default:
LLVM_UNREACHABLE("Unsupported addressing mode!");
llvm_unreachable("Unsupported addressing mode!");
break;
}

6
lib/Target/Alpha/AlphaCodeEmitter.cpp
View File

@ -166,7 +166,7 @@ static unsigned getAlphaRegNumber(unsigned Reg) {
case Alpha::R30 : case Alpha::F30 : return 30;
case Alpha::R31 : case Alpha::F31 : return 31;
default:
LLVM_UNREACHABLE("Unhandled reg");
llvm_unreachable("Unhandled reg");
}
}
@ -217,7 +217,7 @@ unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI,
Offset = MI.getOperand(3).getImm();
break;
default:
LLVM_UNREACHABLE("unknown relocatable instruction");
llvm_unreachable("unknown relocatable instruction");
}
if (MO.isGlobal())
MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
@ -238,7 +238,7 @@ unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI,
#ifndef NDEBUG
cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
#endif
llvm_unreachable();
llvm_unreachable(0);
}
return rv;

8
lib/Target/Alpha/AlphaISelDAGToDAG.cpp
View File

@ -338,7 +338,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDValue Op) {
bool rev = false;
bool inv = false;
switch(CC) {
default: DEBUG(N->dump(CurDAG)); LLVM_UNREACHABLE("Unknown FP comparison!");
default: DEBUG(N->dump(CurDAG)); llvm_unreachable("Unknown FP comparison!");
case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ:
Opc = Alpha::CMPTEQ; break;
case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT:
@ -472,7 +472,7 @@ void AlphaDAGToDAGISel::SelectCALL(SDValue Op) {
} else if (TypeOperands[i] == MVT::f64) {
Opc = Alpha::STT;
} else
LLVM_UNREACHABLE("Unknown operand");
llvm_unreachable("Unknown operand");
SDValue Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8),
CurDAG->getCopyFromReg(Chain, dl, Alpha::R30, MVT::i64),
@ -489,7 +489,7 @@ void AlphaDAGToDAGISel::SelectCALL(SDValue Op) {
CallOperands[i], InFlag);
InFlag = Chain.getValue(1);
} else
LLVM_UNREACHABLE("Unknown operand");
llvm_unreachable("Unknown operand");
}
// Finally, once everything is in registers to pass to the call, emit the
@ -512,7 +512,7 @@ void AlphaDAGToDAGISel::SelectCALL(SDValue Op) {
std::vector<SDValue> CallResults;
switch (N->getValueType(0).getSimpleVT()) {
default: LLVM_UNREACHABLE("Unexpected ret value!");
default: llvm_unreachable("Unexpected ret value!");
case MVT::Other: break;
case MVT::i64:
Chain = CurDAG->getCopyFromReg(Chain, dl,

8
lib/Target/Alpha/AlphaISelLowering.cpp
View File

@ -314,7 +314,7 @@ static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
SDValue());
switch (Op.getNumOperands()) {
default:
LLVM_UNREACHABLE("Do not know how to return this many arguments!");
llvm_unreachable("Do not know how to return this many arguments!");
case 1:
break;
//return SDValue(); // ret void is legal
@ -380,7 +380,7 @@ AlphaTargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
for (unsigned i = 0, e = Args.size(); i != e; ++i)
{
switch (getValueType(Args[i].Ty).getSimpleVT()) {
default: LLVM_UNREACHABLE("Unexpected ValueType for argument!");
default: llvm_unreachable("Unexpected ValueType for argument!");
case MVT::i1:
case MVT::i8:
case MVT::i16:
@ -476,7 +476,7 @@ void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain,
SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
switch (Op.getOpcode()) {
default: LLVM_UNREACHABLE("Wasn't expecting to be able to lower this!");
default: llvm_unreachable("Wasn't expecting to be able to lower this!");
case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
VarArgsBase,
VarArgsOffset);
@ -527,7 +527,7 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
return Lo;
}
case ISD::GlobalTLSAddress:
LLVM_UNREACHABLE("TLS not implemented for Alpha.");
llvm_unreachable("TLS not implemented for Alpha.");
case ISD::GlobalAddress: {
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
GlobalValue *GV = GSDN->getGlobal();

10
lib/Target/Alpha/AlphaInstrInfo.cpp
View File

@ -201,7 +201,7 @@ AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
.addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
else
LLVM_UNREACHABLE("Unhandled register class");
llvm_unreachable("Unhandled register class");
}
void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
@ -217,7 +217,7 @@ void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
else if (RC == Alpha::GPRCRegisterClass)
Opc = Alpha::STQ;
else
LLVM_UNREACHABLE("Unhandled register class");
llvm_unreachable("Unhandled register class");
DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB =
BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
@ -246,7 +246,7 @@ AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
BuildMI(MBB, MI, DL, get(Alpha::LDQ), DestReg)
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
else
LLVM_UNREACHABLE("Unhandled register class");
llvm_unreachable("Unhandled register class");
}
void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
@ -261,7 +261,7 @@ void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
else if (RC == Alpha::GPRCRegisterClass)
Opc = Alpha::LDQ;
else
LLVM_UNREACHABLE("Unhandled register class");
llvm_unreachable("Unhandled register class");
DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB =
BuildMI(MF, DL, get(Opc), DestReg);
@ -332,7 +332,7 @@ static unsigned AlphaRevCondCode(unsigned Opcode) {
case Alpha::FBLE: return Alpha::FBGT;
case Alpha::FBLT: return Alpha::FBGE;
default:
LLVM_UNREACHABLE("Unknown opcode");
llvm_unreachable("Unknown opcode");
}
return 0; // Not reached
}

8
lib/Target/Alpha/AlphaJITInfo.cpp
View File

@ -72,7 +72,7 @@ static void EmitBranchToAt(void *At, void *To) {
void AlphaJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
//FIXME
llvm_unreachable();
llvm_unreachable(0);
}
static TargetJITInfo::JITCompilerFn JITCompilerFunction;
@ -185,7 +185,7 @@ extern "C" {
);
#else
void AlphaCompilationCallback() {
LLVM_UNREACHABLE("Cannot call AlphaCompilationCallback() on a non-Alpha arch!");
llvm_unreachable("Cannot call AlphaCompilationCallback() on a non-Alpha arch!");
}
#endif
}
@ -241,7 +241,7 @@ void AlphaJITInfo::relocate(void *Function, MachineRelocation *MR,
long idx = 0;
bool doCommon = true;
switch ((Alpha::RelocationType)MR->getRelocationType()) {
default: LLVM_UNREACHABLE("Unknown relocation type!");
default: llvm_unreachable("Unknown relocation type!");
case Alpha::reloc_literal:
//This is a LDQl
idx = MR->getGOTIndex();
@ -281,7 +281,7 @@ void AlphaJITInfo::relocate(void *Function, MachineRelocation *MR,
DOUT << "LDA: " << idx << "\n";
break;
default:
LLVM_UNREACHABLE("Cannot handle gpdist yet");
llvm_unreachable("Cannot handle gpdist yet");
}
break;
case Alpha::reloc_bsr: {

8
lib/Target/Alpha/AlphaRegisterInfo.cpp
View File

@ -307,7 +307,7 @@ void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
}
unsigned AlphaRegisterInfo::getRARegister() const {
LLVM_UNREACHABLE("What is the return address register");
llvm_unreachable("What is the return address register");
return 0;
}
@ -316,17 +316,17 @@ unsigned AlphaRegisterInfo::getFrameRegister(MachineFunction &MF) const {
}
unsigned AlphaRegisterInfo::getEHExceptionRegister() const {
LLVM_UNREACHABLE("What is the exception register");
llvm_unreachable("What is the exception register");
return 0;
}
unsigned AlphaRegisterInfo::getEHHandlerRegister() const {
LLVM_UNREACHABLE("What is the exception handler register");
llvm_unreachable("What is the exception handler register");
return 0;
}
int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
LLVM_UNREACHABLE("What is the dwarf register number");
llvm_unreachable("What is the dwarf register number");
return -1;
}

8
lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
View File

@ -101,7 +101,7 @@ void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
return;
case MachineOperand::MO_Immediate:
LLVM_UNREACHABLE("printOp() does not handle immediate values");
llvm_unreachable("printOp() does not handle immediate values");
return;
case MachineOperand::MO_MachineBasicBlock:
@ -155,7 +155,7 @@ bool AlphaAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
EmitAlignment(MF.getAlignment(), F);
switch (F->getLinkage()) {
default: LLVM_UNREACHABLE("Unknown linkage type!");
default: llvm_unreachable("Unknown linkage type!");
case Function::InternalLinkage: // Symbols default to internal.
case Function::PrivateLinkage:
break;
@ -188,7 +188,7 @@ bool AlphaAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
// Print the assembly for the instruction.
++EmittedInsts;
if (!printInstruction(II)) {
LLVM_UNREACHABLE("Unhandled instruction in asm writer!");
llvm_unreachable("Unhandled instruction in asm writer!");
}
}
}
@ -248,7 +248,7 @@ void AlphaAsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) {
case GlobalValue::PrivateLinkage:
break;
default:
LLVM_UNREACHABLE("Unknown linkage type!");
llvm_unreachable("Unknown linkage type!");
}
// 3: Type, Size, Align

44
lib/Target/CBackend/CBackend.cpp
View File

@ -289,11 +289,11 @@ namespace {
void visitBranchInst(BranchInst &I);
void visitSwitchInst(SwitchInst &I);
void visitInvokeInst(InvokeInst &I) {
LLVM_UNREACHABLE("Lowerinvoke pass didn't work!");
llvm_unreachable("Lowerinvoke pass didn't work!");
}
void visitUnwindInst(UnwindInst &I) {
LLVM_UNREACHABLE("Lowerinvoke pass didn't work!");
llvm_unreachable("Lowerinvoke pass didn't work!");
}
void visitUnreachableInst(UnreachableInst &I);
@ -327,7 +327,7 @@ namespace {
#ifndef NDEBUG
cerr << "C Writer does not know about " << I;
#endif
llvm_unreachable();
llvm_unreachable(0);
}
void outputLValue(Instruction *I) {
@ -513,7 +513,7 @@ CWriter::printSimpleType(raw_ostream &Out, const Type *Ty, bool isSigned,
#ifndef NDEBUG
cerr << "Unknown primitive type: " << *Ty << "\n";
#endif
llvm_unreachable();
llvm_unreachable(0);
}
}
@ -560,7 +560,7 @@ CWriter::printSimpleType(std::ostream &Out, const Type *Ty, bool isSigned,
#ifndef NDEBUG
cerr << "Unknown primitive type: " << *Ty << "\n";
#endif
llvm_unreachable();
llvm_unreachable(0);
}
}
@ -661,7 +661,7 @@ raw_ostream &CWriter::printType(raw_ostream &Out, const Type *Ty,
return Out << TyName << ' ' << NameSoFar;
}
default:
LLVM_UNREACHABLE("Unhandled case in getTypeProps!");
llvm_unreachable("Unhandled case in getTypeProps!");
}
return Out;
@ -764,7 +764,7 @@ std::ostream &CWriter::printType(std::ostream &Out, const Type *Ty,
return Out << TyName << ' ' << NameSoFar;
}
default:
LLVM_UNREACHABLE("Unhandled case in getTypeProps!");
llvm_unreachable("Unhandled case in getTypeProps!");
}
return Out;
@ -923,7 +923,7 @@ void CWriter::printCast(unsigned opc, const Type *SrcTy, const Type *DstTy) {
Out << ')';
break;
default:
LLVM_UNREACHABLE("Invalid cast opcode");
llvm_unreachable("Invalid cast opcode");
}
// Print the source type cast
@ -953,7 +953,7 @@ void CWriter::printCast(unsigned opc, const Type *SrcTy, const Type *DstTy) {
case Instruction::FPToUI:
break; // These don't need a source cast.
default:
LLVM_UNREACHABLE("Invalid cast opcode");
llvm_unreachable("Invalid cast opcode");
break;
}
}
@ -1062,10 +1062,10 @@ void CWriter::printConstant(Constant *CPV, bool Static) {
case ICmpInst::ICMP_UGT: Out << " > "; break;
case ICmpInst::ICMP_SGE:
case ICmpInst::ICMP_UGE: Out << " >= "; break;
default: LLVM_UNREACHABLE("Illegal ICmp predicate");
default: llvm_unreachable("Illegal ICmp predicate");
}
break;
default: LLVM_UNREACHABLE("Illegal opcode here!");
default: llvm_unreachable("Illegal opcode here!");
}
printConstantWithCast(CE->getOperand(1), CE->getOpcode());
if (NeedsClosingParens)
@ -1083,7 +1083,7 @@ void CWriter::printConstant(Constant *CPV, bool Static) {
else {
const char* op = 0;
switch (CE->getPredicate()) {
default: LLVM_UNREACHABLE("Illegal FCmp predicate");
default: llvm_unreachable("Illegal FCmp predicate");
case FCmpInst::FCMP_ORD: op = "ord"; break;
case FCmpInst::FCMP_UNO: op = "uno"; break;
case FCmpInst::FCMP_UEQ: op = "ueq"; break;
@ -1115,7 +1115,7 @@ void CWriter::printConstant(Constant *CPV, bool Static) {
cerr << "CWriter Error: Unhandled constant expression: "
<< *CE << "\n";
#endif
llvm_unreachable();
llvm_unreachable(0);
}
} else if (isa<UndefValue>(CPV) && CPV->getType()->isSingleValueType()) {
Out << "((";
@ -1324,7 +1324,7 @@ void CWriter::printConstant(Constant *CPV, bool Static) {
#ifndef NDEBUG
cerr << "Unknown constant type: " << *CPV << "\n";
#endif
llvm_unreachable();
llvm_unreachable(0);
}
}
@ -2128,7 +2128,7 @@ void CWriter::printFloatingPointConstants(const Constant *C) {
<< "}; /* Long double constant */\n";
} else {
LLVM_UNREACHABLE("Unknown float type!");
llvm_unreachable("Unknown float type!");
}
}
@ -2680,7 +2680,7 @@ void CWriter::visitBinaryOperator(Instruction &I) {
#ifndef NDEBUG
cerr << "Invalid operator type!" << I;
#endif
llvm_unreachable();
llvm_unreachable(0);
}
writeOperandWithCast(I.getOperand(1), I.getOpcode());
@ -2721,7 +2721,7 @@ void CWriter::visitICmpInst(ICmpInst &I) {
#ifndef NDEBUG
cerr << "Invalid icmp predicate!" << I;
#endif
llvm_unreachable();
llvm_unreachable(0);
}
writeOperandWithCast(I.getOperand(1), I);
@ -2745,7 +2745,7 @@ void CWriter::visitFCmpInst(FCmpInst &I) {
const char* op = 0;
switch (I.getPredicate()) {
default: LLVM_UNREACHABLE("Illegal FCmp predicate");
default: llvm_unreachable("Illegal FCmp predicate");
case FCmpInst::FCMP_ORD: op = "ord"; break;
case FCmpInst::FCMP_UNO: op = "uno"; break;
case FCmpInst::FCMP_UEQ: op = "ueq"; break;
@ -2773,7 +2773,7 @@ void CWriter::visitFCmpInst(FCmpInst &I) {
static const char * getFloatBitCastField(const Type *Ty) {
switch (Ty->getTypeID()) {
default: LLVM_UNREACHABLE("Invalid Type");
default: llvm_unreachable("Invalid Type");
case Type::FloatTyID: return "Float";
case Type::DoubleTyID: return "Double";
case Type::IntegerTyID: {
@ -3136,7 +3136,7 @@ bool CWriter::visitBuiltinCall(CallInst &I, Intrinsic::ID ID,
Out << ')';
// Multiple GCC builtins multiplex onto this intrinsic.
switch (cast<ConstantInt>(I.getOperand(3))->getZExtValue()) {
default: LLVM_UNREACHABLE("Invalid llvm.x86.sse.cmp!");
default: llvm_unreachable("Invalid llvm.x86.sse.cmp!");
case 0: Out << "__builtin_ia32_cmpeq"; break;
case 1: Out << "__builtin_ia32_cmplt"; break;
case 2: Out << "__builtin_ia32_cmple"; break;
@ -3348,7 +3348,7 @@ void CWriter::visitInlineAsm(CallInst &CI) {
}
void CWriter::visitMallocInst(MallocInst &I) {
LLVM_UNREACHABLE("lowerallocations pass didn't work!");
llvm_unreachable("lowerallocations pass didn't work!");
}
void CWriter::visitAllocaInst(AllocaInst &I) {
@ -3365,7 +3365,7 @@ void CWriter::visitAllocaInst(AllocaInst &I) {
}
void CWriter::visitFreeInst(FreeInst &I) {
LLVM_UNREACHABLE("lowerallocations pass didn't work!");
llvm_unreachable("lowerallocations pass didn't work!");
}
void CWriter::printGEPExpression(Value *Ptr, gep_type_iterator I,

6
lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
View File

@ -265,7 +265,7 @@ namespace {
&& "Invalid negated immediate rotate 7-bit argument");
O << -value;
} else {
LLVM_UNREACHABLE("Invalid/non-immediate rotate amount in printRotateNeg7Imm");
llvm_unreachable("Invalid/non-immediate rotate amount in printRotateNeg7Imm");
}
}
@ -276,7 +276,7 @@ namespace {
&& "Invalid negated immediate rotate 7-bit argument");
O << -value;
} else {
LLVM_UNREACHABLE("Invalid/non-immediate rotate amount in printRotateNeg7Imm");
llvm_unreachable("Invalid/non-immediate rotate amount in printRotateNeg7Imm");
}
}
@ -434,7 +434,7 @@ LinuxAsmPrinter::runOnMachineFunction(MachineFunction &MF)
EmitAlignment(MF.getAlignment(), F);
switch (F->getLinkage()) {
default: LLVM_UNREACHABLE("Unknown linkage type!");
default: llvm_unreachable("Unknown linkage type!");
case Function::PrivateLinkage:
case Function::InternalLinkage: // Symbols default to internal.
break;

2
lib/Target/CellSPU/SPUISelDAGToDAG.cpp
View File

@ -378,7 +378,7 @@ namespace {
break;
case 'v': // not offsetable
#if 1
LLVM_UNREACHABLE("InlineAsmMemoryOperand 'v' constraint not handled.");
llvm_unreachable("InlineAsmMemoryOperand 'v' constraint not handled.");
#else
SelectAddrIdxOnly(Op, Op, Op0, Op1);
#endif

26
lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -875,7 +875,7 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
}
}
LLVM_UNREACHABLE("LowerConstantPool: Relocation model other than static"
llvm_unreachable("LowerConstantPool: Relocation model other than static"
" not supported.");
return SDValue();
}
@ -906,7 +906,7 @@ LowerJumpTable(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
}
}
LLVM_UNREACHABLE("LowerJumpTable: Relocation model other than static"
llvm_unreachable("LowerJumpTable: Relocation model other than static"
" not supported.");
return SDValue();
}
@ -1138,7 +1138,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
switch (Arg.getValueType().getSimpleVT()) {
default: LLVM_UNREACHABLE("Unexpected ValueType for argument!");
default: llvm_unreachable("Unexpected ValueType for argument!");
case MVT::i8:
case MVT::i16:
case MVT::i32:
@ -1270,7 +1270,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
// If the call has results, copy the values out of the ret val registers.
switch (TheCall->getValueType(0).getSimpleVT()) {
default: LLVM_UNREACHABLE("Unexpected ret value!");
default: llvm_unreachable("Unexpected ret value!");
case MVT::Other: break;
case MVT::i32:
if (TheCall->getValueType(1) == MVT::i32) {
@ -1738,7 +1738,7 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
} else if (EltVT == MVT::i64 || EltVT == MVT::f64) {
V2EltIdx0 = 2;
} else
LLVM_UNREACHABLE("Unhandled vector type in LowerVECTOR_SHUFFLE");
llvm_unreachable("Unhandled vector type in LowerVECTOR_SHUFFLE");
for (unsigned i = 0; i != MaxElts; ++i) {
if (SVN->getMaskElt(i) < 0)
@ -1834,7 +1834,7 @@ static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
// Create a constant vector:
switch (Op.getValueType().getSimpleVT()) {
default: LLVM_UNREACHABLE("Unexpected constant value type in "
default: llvm_unreachable("Unexpected constant value type in "
"LowerSCALAR_TO_VECTOR");
case MVT::v16i8: n_copies = 16; VT = MVT::i8; break;
case MVT::v8i16: n_copies = 8; VT = MVT::i16; break;
@ -1853,7 +1853,7 @@ static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
} else {
// Otherwise, copy the value from one register to another:
switch (Op0.getValueType().getSimpleVT()) {
default: LLVM_UNREACHABLE("Unexpected value type in LowerSCALAR_TO_VECTOR");
default: llvm_unreachable("Unexpected value type in LowerSCALAR_TO_VECTOR");
case MVT::i8:
case MVT::i16:
case MVT::i32:
@ -1880,13 +1880,13 @@ static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
// sanity checks:
if (VT == MVT::i8 && EltNo >= 16)
LLVM_UNREACHABLE("SPU LowerEXTRACT_VECTOR_ELT: i8 extraction slot > 15");
llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i8 extraction slot > 15");
else if (VT == MVT::i16 && EltNo >= 8)
LLVM_UNREACHABLE("SPU LowerEXTRACT_VECTOR_ELT: i16 extraction slot > 7");
llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i16 extraction slot > 7");
else if (VT == MVT::i32 && EltNo >= 4)
LLVM_UNREACHABLE("SPU LowerEXTRACT_VECTOR_ELT: i32 extraction slot > 4");
llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i32 extraction slot > 4");
else if (VT == MVT::i64 && EltNo >= 2)
LLVM_UNREACHABLE("SPU LowerEXTRACT_VECTOR_ELT: i64 extraction slot > 2");
llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i64 extraction slot > 2");
if (EltNo == 0 && (VT == MVT::i32 || VT == MVT::i64)) {
// i32 and i64: Element 0 is the preferred slot
@ -2065,7 +2065,7 @@ static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc,
assert(Op.getValueType() == MVT::i8);
switch (Opc) {
default:
LLVM_UNREACHABLE("Unhandled i8 math operator");
llvm_unreachable("Unhandled i8 math operator");
/*NOTREACHED*/
break;
case ISD::ADD: {
@ -2585,7 +2585,7 @@ SPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
cerr << "*Op.getNode():\n";
Op.getNode()->dump();
#endif
llvm_unreachable();
llvm_unreachable(0);
}
case ISD::LOAD:
case ISD::EXTLOAD:

8
lib/Target/CellSPU/SPUInstrInfo.cpp
View File

@ -314,7 +314,7 @@ SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
} else if (RC == SPU::VECREGRegisterClass) {
opc = (isValidFrameIdx) ? SPU::STQDv16i8 : SPU::STQXv16i8;
} else {
LLVM_UNREACHABLE("Unknown regclass!");
llvm_unreachable("Unknown regclass!");
}
DebugLoc DL = DebugLoc::getUnknownLoc();
@ -347,7 +347,7 @@ void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
} else if (RC == SPU::VECREGRegisterClass) {
/* Opc = PPC::STVX; */
} else {
LLVM_UNREACHABLE("Unknown regclass!");
llvm_unreachable("Unknown regclass!");
}
DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
@ -383,7 +383,7 @@ SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
} else if (RC == SPU::VECREGRegisterClass) {
opc = (isValidFrameIdx) ? SPU::LQDv16i8 : SPU::LQXv16i8;
} else {
LLVM_UNREACHABLE("Unknown regclass in loadRegFromStackSlot!");
llvm_unreachable("Unknown regclass in loadRegFromStackSlot!");
}
DebugLoc DL = DebugLoc::getUnknownLoc();
@ -420,7 +420,7 @@ void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
} else if (RC == SPU::GPRCRegisterClass) {
/* Opc = something else! */
} else {
LLVM_UNREACHABLE("Unknown regclass!");
llvm_unreachable("Unknown regclass!");
}
DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);

4
lib/Target/CppBackend/CPPBackend.cpp
View File

@ -325,7 +325,7 @@ namespace {
void CppWriter::printVisibilityType(GlobalValue::VisibilityTypes VisType) {
switch (VisType) {
default: LLVM_UNREACHABLE("Unknown GVar visibility");
default: llvm_unreachable("Unknown GVar visibility");
case GlobalValue::DefaultVisibility:
Out << "GlobalValue::DefaultVisibility";
break;
@ -844,7 +844,7 @@ namespace {
printConstant(CE->getOperand(0));
Out << "Constant* " << constName << " = ConstantExpr::getCast(";
switch (CE->getOpcode()) {
default: LLVM_UNREACHABLE("Invalid cast opcode");
default: llvm_unreachable("Invalid cast opcode");
case Instruction::Trunc: Out << "Instruction::Trunc"; break;
case Instruction::ZExt: Out << "Instruction::ZExt"; break;
case Instruction::SExt: Out << "Instruction::SExt"; break;

4
lib/Target/DarwinTargetAsmInfo.cpp
View File

@ -152,7 +152,7 @@ DarwinTargetAsmInfo::SelectSectionForGlobal(const GlobalValue *GV) const {
ConstDataCoalSection:
MergeableConstSection(cast<GlobalVariable>(GV)));
default:
LLVM_UNREACHABLE("Unsuported section kind for global");
llvm_unreachable("Unsuported section kind for global");
}
// FIXME: Do we have any extra special weird cases?
@ -212,6 +212,6 @@ DarwinTargetAsmInfo::SelectSectionForMachineConst(const Type *Ty) const {
std::string
DarwinTargetAsmInfo::UniqueSectionForGlobal(const GlobalValue* GV,
SectionKind::Kind kind) const {
LLVM_UNREACHABLE("Darwin does not use unique sections");
llvm_unreachable("Darwin does not use unique sections");
return "";
}

6
lib/Target/ELFTargetAsmInfo.cpp
View File

@ -75,7 +75,7 @@ ELFTargetAsmInfo::SelectSectionForGlobal(const GlobalValue *GV) const {
if (const Function *F = dyn_cast<Function>(GV)) {
switch (F->getLinkage()) {
default: LLVM_UNREACHABLE("Unknown linkage type!");
default: llvm_unreachable("Unknown linkage type!");
case Function::PrivateLinkage:
case Function::InternalLinkage:
case Function::DLLExportLinkage:
@ -124,11 +124,11 @@ ELFTargetAsmInfo::SelectSectionForGlobal(const GlobalValue *GV) const {
case SectionKind::ThreadBSS:
return TLSBSSSection;
default:
LLVM_UNREACHABLE("Unsuported section kind for global");
llvm_unreachable("Unsuported section kind for global");
}
}
} else
LLVM_UNREACHABLE("Unsupported global");
llvm_unreachable("Unsupported global");
return NULL;
}

8
lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
View File

@ -318,13 +318,13 @@ void IA64AsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) {
case GlobalValue::PrivateLinkage:
break;
case GlobalValue::GhostLinkage:
LLVM_UNREACHABLE("GhostLinkage cannot appear in IA64AsmPrinter!");
llvm_unreachable("GhostLinkage cannot appear in IA64AsmPrinter!");
case GlobalValue::DLLImportLinkage:
LLVM_UNREACHABLE("DLLImport linkage is not supported by this target!");
llvm_unreachable("DLLImport linkage is not supported by this target!");
case GlobalValue::DLLExportLinkage:
LLVM_UNREACHABLE("DLLExport linkage is not supported by this target!");
llvm_unreachable("DLLExport linkage is not supported by this target!");
default:
LLVM_UNREACHABLE("Unknown linkage type!");
llvm_unreachable("Unknown linkage type!");
}
EmitAlignment(Align, GVar);

10
lib/Target/IA64/IA64ISelDAGToDAG.cpp
View File

@ -215,7 +215,7 @@ SDNode *IA64DAGToDAGISel::SelectDIV(SDValue Op) {
if(isFP) { // if this is an FP divide, we finish up here and exit early
if(isModulus)
LLVM_UNREACHABLE("Sorry, try another FORTRAN compiler.");
llvm_unreachable("Sorry, try another FORTRAN compiler.");
SDValue TmpE2, TmpY3, TmpQ0, TmpR0;
@ -406,7 +406,7 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) {
APFloat(+1.0f) : APFloat(+1.0))) {
V = CurDAG->getCopyFromReg(Chain, dl, IA64::F1, MVT::f64);
} else
LLVM_UNREACHABLE("Unexpected FP constant!");
llvm_unreachable("Unexpected FP constant!");
ReplaceUses(SDValue(N, 0), V);
return 0;
@ -468,7 +468,7 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) {
#ifndef NDEBUG
N->dump(CurDAG);
#endif
LLVM_UNREACHABLE("Cannot load this type!");
llvm_unreachable("Cannot load this type!");
case MVT::i1: { // this is a bool
Opc = IA64::LD1; // first we load a byte, then compare for != 0
if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
@ -504,7 +504,7 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) {
unsigned Opc;
if (ISD::isNON_TRUNCStore(N)) {
switch (N->getOperand(1).getValueType().getSimpleVT()) {
default: LLVM_UNREACHABLE("unknown type in store");
default: llvm_unreachable("unknown type in store");
case MVT::i1: { // this is a bool
Opc = IA64::ST1; // we store either 0 or 1 as a byte
// first load zero!
@ -524,7 +524,7 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) {
}
} else { // Truncating store
switch(ST->getMemoryVT().getSimpleVT()) {
default: LLVM_UNREACHABLE("unknown type in truncstore");
default: llvm_unreachable("unknown type in truncstore");
case MVT::i8: Opc = IA64::ST1; break;
case MVT::i16: Opc = IA64::ST2; break;
case MVT::i32: Opc = IA64::ST4; break;

16
lib/Target/IA64/IA64ISelLowering.cpp
View File

@ -194,7 +194,7 @@ void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
switch (getValueType(I->getType()).getSimpleVT()) {
default:
LLVM_UNREACHABLE("ERROR in LowerArgs: can't lower this type of arg.");
llvm_unreachable("ERROR in LowerArgs: can't lower this type of arg.");
case MVT::f32:
// fixme? (well, will need to for weird FP structy stuff,
// see intel ABI docs)
@ -298,7 +298,7 @@ void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
// Finally, inform the code generator which regs we return values in.
// (see the ISD::RET: case in the instruction selector)
switch (getValueType(F.getReturnType()).getSimpleVT()) {
default: LLVM_UNREACHABLE("i have no idea where to return this type!");
default: llvm_unreachable("i have no idea where to return this type!");
case MVT::isVoid: break;
case MVT::i1:
case MVT::i8:
@ -362,7 +362,7 @@ IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
SDValue ValToStore(0, 0), ValToConvert(0, 0);
unsigned ObjSize=8;
switch (ObjectVT.getSimpleVT()) {
default: LLVM_UNREACHABLE("unexpected argument type!");
default: llvm_unreachable("unexpected argument type!");
case MVT::i1:
case MVT::i8:
case MVT::i16:
@ -493,7 +493,7 @@ IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
if (InFlag.getNode())
CallOperands.push_back(InFlag);
else
LLVM_UNREACHABLE("this should never happen!");
llvm_unreachable("this should never happen!");
// to make way for a hack:
Chain = DAG.getNode(IA64ISD::BRCALL, dl, NodeTys,
@ -516,7 +516,7 @@ IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
SDValue RetVal;
if (RetTyVT != MVT::isVoid) {
switch (RetTyVT.getSimpleVT()) {
default: LLVM_UNREACHABLE("Unknown value type to return!");
default: llvm_unreachable("Unknown value type to return!");
case MVT::i1: { // bools are just like other integers (returned in r8)
// we *could* fall through to the truncate below, but this saves a
// few redundant predicate ops
@ -573,15 +573,15 @@ SDValue IA64TargetLowering::
LowerOperation(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
switch (Op.getOpcode()) {
default: LLVM_UNREACHABLE("Should not custom lower this!");
default: llvm_unreachable("Should not custom lower this!");
case ISD::GlobalTLSAddress:
LLVM_UNREACHABLE("TLS not implemented for IA64.");
llvm_unreachable("TLS not implemented for IA64.");
case ISD::RET: {
SDValue AR_PFSVal, Copy;
switch(Op.getNumOperands()) {
default:
LLVM_UNREACHABLE("Do not know how to return this many arguments!");
llvm_unreachable("Do not know how to return this many arguments!");
case 1:
AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), dl, VirtGPR, MVT::i64);
AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), dl, IA64::AR_PFS,

8
lib/Target/IA64/IA64InstrInfo.cpp
View File

@ -113,7 +113,7 @@ void IA64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
.addFrameIndex(FrameIdx)
.addReg(IA64::r2);
} else
LLVM_UNREACHABLE("sorry, I don't know how to store this sort of reg"
llvm_unreachable("sorry, I don't know how to store this sort of reg"
"in the stack");
}
@ -130,7 +130,7 @@ void IA64InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
} else if (RC == IA64::PRRegisterClass) {
Opc = IA64::ST1;
} else {
LLVM_UNREACHABLE("sorry, I don't know how to store this sort of reg");
llvm_unreachable("sorry, I don't know how to store this sort of reg");
}
DebugLoc DL = DebugLoc::getUnknownLoc();
@ -164,7 +164,7 @@ void IA64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
.addReg(IA64::r2)
.addReg(IA64::r0);
} else {
LLVM_UNREACHABLE("sorry, I don't know how to load this sort of reg"
llvm_unreachable("sorry, I don't know how to load this sort of reg"
"from the stack");
}
}
@ -181,7 +181,7 @@ void IA64InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
} else if (RC == IA64::PRRegisterClass) {
Opc = IA64::LD1;
} else {
LLVM_UNREACHABLE("sorry, I don't know how to load this sort of reg");
llvm_unreachable("sorry, I don't know how to load this sort of reg");
}
DebugLoc DL = DebugLoc::getUnknownLoc();

8
lib/Target/IA64/IA64RegisterInfo.cpp
View File

@ -293,7 +293,7 @@ void IA64RegisterInfo::emitEpilogue(MachineFunction &MF,
}
unsigned IA64RegisterInfo::getRARegister() const {
LLVM_UNREACHABLE("What is the return address register");
llvm_unreachable("What is the return address register");
return 0;
}
@ -302,17 +302,17 @@ unsigned IA64RegisterInfo::getFrameRegister(MachineFunction &MF) const {
}
unsigned IA64RegisterInfo::getEHExceptionRegister() const {
LLVM_UNREACHABLE("What is the exception register");
llvm_unreachable("What is the exception register");
return 0;
}
unsigned IA64RegisterInfo::getEHHandlerRegister() const {
LLVM_UNREACHABLE("What is the exception handler register");
llvm_unreachable("What is the exception handler register");
return 0;
}
int IA64RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
LLVM_UNREACHABLE("What is the dwarf register number");
llvm_unreachable("What is the dwarf register number");
return -1;
}

48
lib/Target/MSIL/MSILWriter.cpp
View File

@ -292,7 +292,7 @@ std::string MSILWriter::getConvModopt(unsigned CallingConvID) {
return "modopt([mscorlib]System.Runtime.CompilerServices.CallConvStdcall) ";
default:
cerr << "CallingConvID = " << CallingConvID << '\n';
LLVM_UNREACHABLE("Unsupported calling convention");
llvm_unreachable("Unsupported calling convention");
}
return ""; // Not reached
}
@ -338,7 +338,7 @@ std::string MSILWriter::getPrimitiveTypeName(const Type* Ty, bool isSigned) {
return "float64 ";
default:
cerr << "Type = " << *Ty << '\n';
LLVM_UNREACHABLE("Invalid primitive type");
llvm_unreachable("Invalid primitive type");
}
return ""; // Not reached
}
@ -366,7 +366,7 @@ std::string MSILWriter::getTypeName(const Type* Ty, bool isSigned,
return "valuetype '"+getArrayTypeName(Ty->getTypeID(),Ty)+"' ";
default:
cerr << "Type = " << *Ty << '\n';
LLVM_UNREACHABLE("Invalid type in getTypeName()");
llvm_unreachable("Invalid type in getTypeName()");
}
return ""; // Not reached
}
@ -410,7 +410,7 @@ std::string MSILWriter::getTypePostfix(const Type* Ty, bool Expand,
return "i"+utostr(TD->getTypeAllocSize(Ty));
default:
cerr << "TypeID = " << Ty->getTypeID() << '\n';
LLVM_UNREACHABLE("Invalid type in TypeToPostfix()");
llvm_unreachable("Invalid type in TypeToPostfix()");
}
return ""; // Not reached
}
@ -425,7 +425,7 @@ void MSILWriter::printConvToPtr() {
printSimpleInstruction("conv.u8");
break;
default:
LLVM_UNREACHABLE("Module use not supporting pointer size");
llvm_unreachable("Module use not supporting pointer size");
}
}
@ -437,14 +437,14 @@ void MSILWriter::printPtrLoad(uint64_t N) {
// FIXME: Need overflow test?
if (!isUInt32(N)) {
cerr << "Value = " << utostr(N) << '\n';
LLVM_UNREACHABLE("32-bit pointer overflowed");
llvm_unreachable("32-bit pointer overflowed");
}
break;
case Module::Pointer64:
printSimpleInstruction("ldc.i8",utostr(N).c_str());
break;
default:
LLVM_UNREACHABLE("Module use not supporting pointer size");
llvm_unreachable("Module use not supporting pointer size");
}
}
@ -480,7 +480,7 @@ void MSILWriter::printConstLoad(const Constant* C) {
printPtrLoad(0);
} else {
cerr << "Constant = " << *C << '\n';
LLVM_UNREACHABLE("Invalid constant value");
llvm_unreachable("Invalid constant value");
}
Out << '\n';
}
@ -529,7 +529,7 @@ void MSILWriter::printValueLoad(const Value* V) {
break;
default:
cerr << "Value = " << *V << '\n';
LLVM_UNREACHABLE("Invalid value location");
llvm_unreachable("Invalid value location");
}
}
@ -544,7 +544,7 @@ void MSILWriter::printValueSave(const Value* V) {
break;
default:
cerr << "Value = " << *V << '\n';
LLVM_UNREACHABLE("Invalid value location");
llvm_unreachable("Invalid value location");
}
}
@ -705,7 +705,7 @@ void MSILWriter::printCastInstruction(unsigned int Op, const Value* V,
break;
default:
cerr << "Opcode = " << Op << '\n';
LLVM_UNREACHABLE("Invalid conversion instruction");
llvm_unreachable("Invalid conversion instruction");
}
}
@ -796,7 +796,7 @@ void MSILWriter::printFunctionCall(const Value* FnVal,
Name = getConvModopt(Invoke->getCallingConv());
else {
cerr << "Instruction = " << Inst->getName() << '\n';
LLVM_UNREACHABLE("Need \"Invoke\" or \"Call\" instruction only");
llvm_unreachable("Need \"Invoke\" or \"Call\" instruction only");
}
if (const Function* F = dyn_cast<Function>(FnVal)) {
// Direct call.
@ -844,7 +844,7 @@ void MSILWriter::printIntrinsicCall(const IntrinsicInst* Inst) {
break;
default:
cerr << "Intrinsic ID = " << Inst->getIntrinsicID() << '\n';
LLVM_UNREACHABLE("Invalid intrinsic function");
llvm_unreachable("Invalid intrinsic function");
}
}
@ -908,7 +908,7 @@ void MSILWriter::printICmpInstruction(unsigned Predicate, const Value* Left,
break;
default:
cerr << "Predicate = " << Predicate << '\n';
LLVM_UNREACHABLE("Invalid icmp predicate");
llvm_unreachable("Invalid icmp predicate");
}
}
@ -1002,7 +1002,7 @@ void MSILWriter::printFCmpInstruction(unsigned Predicate, const Value* Left,
printSimpleInstruction("or");
break;
default:
LLVM_UNREACHABLE("Illegal FCmp predicate");
llvm_unreachable("Illegal FCmp predicate");
}
}
@ -1199,10 +1199,10 @@ void MSILWriter::printInstruction(const Instruction* Inst) {
printAllocaInstruction(cast<AllocaInst>(Inst));
break;
case Instruction::Malloc:
LLVM_UNREACHABLE("LowerAllocationsPass used");
llvm_unreachable("LowerAllocationsPass used");
break;
case Instruction::Free:
LLVM_UNREACHABLE("LowerAllocationsPass used");
llvm_unreachable("LowerAllocationsPass used");
break;
case Instruction::Unreachable:
printSimpleInstruction("ldstr", "\"Unreachable instruction\"");
@ -1215,7 +1215,7 @@ void MSILWriter::printInstruction(const Instruction* Inst) {
break;
default:
cerr << "Instruction = " << Inst->getName() << '\n';
LLVM_UNREACHABLE("Unsupported instruction");
llvm_unreachable("Unsupported instruction");
}
}
@ -1403,7 +1403,7 @@ void MSILWriter::printConstantExpr(const ConstantExpr* CE) {
break;
default:
cerr << "Expression = " << *CE << "\n";
LLVM_UNREACHABLE("Invalid constant expression");
llvm_unreachable("Invalid constant expression");
}
}
@ -1437,7 +1437,7 @@ void MSILWriter::printStaticInitializerList() {
printSimpleInstruction(postfix.c_str());
} else {
cerr << "Constant = " << *I->constant << '\n';
LLVM_UNREACHABLE("Invalid static initializer");
llvm_unreachable("Invalid static initializer");
}
}
}
@ -1501,7 +1501,7 @@ unsigned int MSILWriter::getBitWidth(const Type* Ty) {
return N;
default:
cerr << "Bits = " << N << '\n';
LLVM_UNREACHABLE("Unsupported integer width");
llvm_unreachable("Unsupported integer width");
}
return 0; // Not reached
}
@ -1558,12 +1558,12 @@ void MSILWriter::printStaticConstant(const Constant* C, uint64_t& Offset) {
// Null pointer initialization
if (TySize==4) Out << "int32 (0)";
else if (TySize==8) Out << "int64 (0)";
else LLVM_UNREACHABLE("Invalid pointer size");
else llvm_unreachable("Invalid pointer size");
}
break;
default:
cerr << "TypeID = " << Ty->getTypeID() << '\n';
LLVM_UNREACHABLE("Invalid type in printStaticConstant()");
llvm_unreachable("Invalid type in printStaticConstant()");
}
// Increase offset.
Offset += TySize;
@ -1586,7 +1586,7 @@ void MSILWriter::printStaticInitializer(const Constant* C,
break;
default:
cerr << "Type = " << *C << "\n";
LLVM_UNREACHABLE("Invalid constant type");
llvm_unreachable("Invalid constant type");
}
// Print initializer
std::string label = Name;

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