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* Simplify code a bit by breaking the PHI node handling stuff out into a seperate

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function from normal regalloc code
* Make the regalloc for a block a function instead of part of runOnMachineBB, which
  makes it easier to see what's going on in runOnMBB.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5051 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2002-12-15 19:51:14 +00:00
parent afe628c1d6
commit c2db1a95df
1 changed files with 170 additions and 161 deletions
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129
lib/CodeGen/RegAllocSimple.cpp
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@ -60,10 +60,8 @@ namespace {
std::map<unsigned, unsigned> RegsUsed; std::map<unsigned, unsigned> RegsUsed;
std::map<const TargetRegisterClass*, unsigned> RegClassIdx; std::map<const TargetRegisterClass*, unsigned> RegClassIdx;
RegAllocSimple(TargetMachine &tm) : TM(tm), RegAllocSimple(TargetMachine &tm)
RegInfo(tm.getRegisterInfo()), : TM(tm), RegInfo(tm.getRegisterInfo()), PhysRegClasses(RegInfo) {
PhysRegClasses(RegInfo)
{
RegsUsed[RegInfo->getFramePointer()] = 1; RegsUsed[RegInfo->getFramePointer()] = 1;
RegsUsed[RegInfo->getStackPointer()] = 1; RegsUsed[RegInfo->getStackPointer()] = 1;
@ -75,7 +73,8 @@ namespace {
return RegsUsed.find(Reg) == RegsUsed.end(); return RegsUsed.find(Reg) == RegsUsed.end();
} }
/// /// allocateStackSpaceFor - This allocates space for the specified virtual
/// register to be held on the stack.
unsigned allocateStackSpaceFor(unsigned VirtReg, unsigned allocateStackSpaceFor(unsigned VirtReg,
const TargetRegisterClass *regClass); const TargetRegisterClass *regClass);
@ -106,23 +105,23 @@ namespace {
void cleanupAfterFunction() { void cleanupAfterFunction() {
VirtReg2OffsetMap.clear(); VirtReg2OffsetMap.clear();
SSA2PhysRegMap.clear(); SSA2PhysRegMap.clear();
NumBytesAllocated = 4; /* FIXME: This is X86 specific */ NumBytesAllocated = 4; // FIXME: This is X86 specific
} }
/// Moves value from memory into that register /// Moves value from memory into that register
MachineBasicBlock::iterator MachineBasicBlock::iterator
moveUseToReg (MachineBasicBlock *MBB, moveUseToReg (MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, unsigned VirtReg, MachineBasicBlock::iterator I, unsigned VirtReg,
unsigned &PhysReg); unsigned &PhysReg);
/// Saves reg value on the stack (maps virtual register to stack value) /// Saves reg value on the stack (maps virtual register to stack value)
MachineBasicBlock::iterator MachineBasicBlock::iterator
saveVirtRegToStack (MachineBasicBlock *MBB, saveVirtRegToStack (MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, unsigned VirtReg, MachineBasicBlock::iterator I, unsigned VirtReg,
unsigned PhysReg); unsigned PhysReg);
MachineBasicBlock::iterator MachineBasicBlock::iterator
savePhysRegToStack (MachineBasicBlock *MBB, savePhysRegToStack (MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, unsigned PhysReg); MachineBasicBlock::iterator I, unsigned PhysReg);
/// runOnFunction - Top level implementation of instruction selection for /// runOnFunction - Top level implementation of instruction selection for
@ -130,6 +129,13 @@ namespace {
/// ///
bool runOnMachineFunction(MachineFunction &Fn); bool runOnMachineFunction(MachineFunction &Fn);
/// AllocateBasicBlock - Register allocate the specified basic block.
void AllocateBasicBlock(MachineBasicBlock &MBB);
/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
/// in predecessor basic blocks.
void EliminatePHINodes(MachineBasicBlock &MBB);
bool runOnFunction(Function &Fn) { bool runOnFunction(Function &Fn) {
return runOnMachineFunction(MachineFunction::get(&Fn)); return runOnMachineFunction(MachineFunction::get(&Fn));
} }
@ -137,6 +143,8 @@ namespace {
} }
/// allocateStackSpaceFor - This allocates space for the specified virtual
/// register to be held on the stack.
unsigned RegAllocSimple::allocateStackSpaceFor(unsigned VirtReg, unsigned RegAllocSimple::allocateStackSpaceFor(unsigned VirtReg,
const TargetRegisterClass *regClass) const TargetRegisterClass *regClass)
{ {
@ -180,7 +188,7 @@ unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) {
} }
MachineBasicBlock::iterator MachineBasicBlock::iterator
RegAllocSimple::moveUseToReg (MachineBasicBlock *MBB, RegAllocSimple::moveUseToReg (MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned &PhysReg) unsigned VirtReg, unsigned &PhysReg)
{ {
@ -191,13 +199,13 @@ RegAllocSimple::moveUseToReg (MachineBasicBlock *MBB,
PhysReg = getFreeReg(VirtReg); PhysReg = getFreeReg(VirtReg);
// Add move instruction(s) // Add move instruction(s)
return RegInfo->loadRegOffset2Reg(MBB, I, PhysReg, return RegInfo->loadRegOffset2Reg(&MBB, I, PhysReg,
RegInfo->getFramePointer(), RegInfo->getFramePointer(),
-stackOffset, regClass->getDataSize()); -stackOffset, regClass->getDataSize());
} }
MachineBasicBlock::iterator MachineBasicBlock::iterator
RegAllocSimple::saveVirtRegToStack (MachineBasicBlock *MBB, RegAllocSimple::saveVirtRegToStack (MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned PhysReg) unsigned VirtReg, unsigned PhysReg)
{ {
@ -207,13 +215,13 @@ RegAllocSimple::saveVirtRegToStack (MachineBasicBlock *MBB,
unsigned stackOffset = allocateStackSpaceFor(VirtReg, regClass); unsigned stackOffset = allocateStackSpaceFor(VirtReg, regClass);
// Add move instruction(s) // Add move instruction(s)
return RegInfo->storeReg2RegOffset(MBB, I, PhysReg, return RegInfo->storeReg2RegOffset(&MBB, I, PhysReg,
RegInfo->getFramePointer(), RegInfo->getFramePointer(),
-stackOffset, regClass->getDataSize()); -stackOffset, regClass->getDataSize());
} }
MachineBasicBlock::iterator MachineBasicBlock::iterator
RegAllocSimple::savePhysRegToStack (MachineBasicBlock *MBB, RegAllocSimple::savePhysRegToStack (MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
unsigned PhysReg) unsigned PhysReg)
{ {
@ -223,28 +231,18 @@ RegAllocSimple::savePhysRegToStack (MachineBasicBlock *MBB,
unsigned offset = allocateStackSpaceFor(PhysReg, regClass); unsigned offset = allocateStackSpaceFor(PhysReg, regClass);
// Add move instruction(s) // Add move instruction(s)
return RegInfo->storeReg2RegOffset(MBB, I, PhysReg, return RegInfo->storeReg2RegOffset(&MBB, I, PhysReg,
RegInfo->getFramePointer(), RegInfo->getFramePointer(),
offset, regClass->getDataSize()); offset, regClass->getDataSize());
} }
bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) { /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
cleanupAfterFunction(); /// predecessor basic blocks.
void RegAllocSimple::EliminatePHINodes(MachineBasicBlock &MBB) {
unsigned virtualReg, physReg; while (MBB.front()->getOpcode() == 0) {
DEBUG(std::cerr << "Machine Function " << "\n"); MachineInstr *MI = MBB.front();
MF = &Fn;
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
MBB != MBBe; ++MBB)
{
MachineBasicBlock *CurrMBB = &(*MBB);
// Handle PHI instructions specially: add moves to each pred block
while (MBB->front()->getOpcode() == 0) {
MachineInstr *MI = MBB->front();
// get rid of the phi // get rid of the phi
MBB->erase(MBB->begin()); MBB.erase(MBB.begin());
// a preliminary pass that will invalidate any registers that // a preliminary pass that will invalidate any registers that
// are used by the instruction (including implicit uses) // are used by the instruction (including implicit uses)
@ -258,7 +256,8 @@ bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
// If it's a virtual register, allocate a physical one // If it's a virtual register, allocate a physical one
// otherwise, just use whatever register is there now // otherwise, just use whatever register is there now
// note: it MUST be a register -- we're assigning to it // note: it MUST be a register -- we're assigning to it
virtualReg = (unsigned) targetReg.getAllocatedRegNum(); unsigned virtualReg = (unsigned) targetReg.getAllocatedRegNum();
unsigned physReg;
if (targetReg.isVirtualRegister()) { if (targetReg.isVirtualRegister()) {
physReg = getFreeReg(virtualReg); physReg = getFreeReg(virtualReg);
} else { } else {
@ -276,27 +275,25 @@ bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
// Get the MachineBasicBlock equivalent of the BasicBlock that is the // Get the MachineBasicBlock equivalent of the BasicBlock that is the
// source path the phi // source path the phi
MachineBasicBlock *opBlock = MI->getOperand(i).getMachineBasicBlock(); MachineBasicBlock &opBlock = *MI->getOperand(i).getMachineBasicBlock();
MachineBasicBlock::iterator opI = opBlock->end(); MachineBasicBlock::iterator opI = opBlock.end();
MachineInstr *opMI = *(--opI); MachineInstr *opMI = *--opI;
const MachineInstrInfo &MII = TM.getInstrInfo(); const MachineInstrInfo &MII = TM.getInstrInfo();
// must backtrack over ALL the branches in the previous block, until no more
while ((MII.isBranch(opMI->getOpcode()) || MII.isReturn(opMI->getOpcode())) // must backtrack over ALL the branches in the previous block, until no
&& opI != opBlock->begin()) // more
{ while (MII.isBranch(opMI->getOpcode()) && opI != opBlock.begin())
opMI = *(--opI); opMI = *--opI;
}
// move back to the first branch instruction so new instructions // move back to the first branch instruction so new instructions
// are inserted right in front of it and not in front of a non-branch // are inserted right in front of it and not in front of a non-branch
if (!MII.isBranch(opMI->getOpcode()))
++opI; ++opI;
// Retrieve the constant value from this op, move it to target // Retrieve the constant value from this op, move it to target
// register of the phi // register of the phi
if (opVal.getType() == MachineOperand::MO_SignExtendedImmed || if (opVal.isImmediate()) {
opVal.getType() == MachineOperand::MO_UnextendedImmed) opI = RegInfo->moveImm2Reg(&opBlock, opI, physReg,
{
opI = RegInfo->moveImm2Reg(opBlock, opI, physReg,
(unsigned) opVal.getImmedValue(), (unsigned) opVal.getImmedValue(),
dataSize); dataSize);
saveVirtRegToStack(opBlock, opI, virtualReg, physReg); saveVirtRegToStack(opBlock, opI, virtualReg, physReg);
@ -318,10 +315,15 @@ bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
// really delete the instruction // really delete the instruction
delete MI; delete MI;
} }
}
void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
// Handle PHI instructions specially: add moves to each pred block
EliminatePHINodes(MBB);
//loop over each basic block //loop over each basic block
for (MachineBasicBlock::iterator I = MBB->begin(); I != MBB->end(); ++I) for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) {
{
MachineInstr *MI = *I; MachineInstr *MI = *I;
// a preliminary pass that will invalidate any registers that // a preliminary pass that will invalidate any registers that
@ -332,18 +334,17 @@ bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
for (int i = MI->getNumOperands() - 1; i >= 0; --i) { for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
MachineOperand &op = MI->getOperand(i); MachineOperand &op = MI->getOperand(i);
if (op.getType() == MachineOperand::MO_SignExtendedImmed || if (op.isImmediate()) {
op.getType() == MachineOperand::MO_UnextendedImmed)
{
DEBUG(std::cerr << "const\n"); DEBUG(std::cerr << "const\n");
} else if (op.isVirtualRegister()) { } else if (op.isVirtualRegister()) {
virtualReg = (unsigned) op.getAllocatedRegNum(); unsigned virtualReg = (unsigned) op.getAllocatedRegNum();
DEBUG(std::cerr << "op: " << op << "\n"); DEBUG(std::cerr << "op: " << op << "\n");
DEBUG(std::cerr << "\t inst[" << i << "]: "; DEBUG(std::cerr << "\t inst[" << i << "]: ";
MI->print(std::cerr, TM)); MI->print(std::cerr, TM));
// make sure the same virtual register maps to the same physical // make sure the same virtual register maps to the same physical
// register in any given instruction // register in any given instruction
unsigned physReg;
if (VirtReg2PhysRegMap.find(virtualReg) != VirtReg2PhysRegMap.end()) { if (VirtReg2PhysRegMap.find(virtualReg) != VirtReg2PhysRegMap.end()) {
physReg = VirtReg2PhysRegMap[virtualReg]; physReg = VirtReg2PhysRegMap[virtualReg];
} else { } else {
@ -356,10 +357,10 @@ bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
physReg = getFreeReg(virtualReg); physReg = getFreeReg(virtualReg);
} }
MachineBasicBlock::iterator J = I; MachineBasicBlock::iterator J = I;
J = saveVirtRegToStack(CurrMBB, ++J, virtualReg, physReg); J = saveVirtRegToStack(MBB, ++J, virtualReg, physReg);
I = --J; I = --J;
} else { } else {
I = moveUseToReg(CurrMBB, I, virtualReg, physReg); I = moveUseToReg(MBB, I, virtualReg, physReg);
} }
VirtReg2PhysRegMap[virtualReg] = physReg; VirtReg2PhysRegMap[virtualReg] = physReg;
} }
@ -372,8 +373,15 @@ bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
clearAllRegs(); clearAllRegs();
VirtReg2PhysRegMap.clear(); VirtReg2PhysRegMap.clear();
} }
}
} bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
DEBUG(std::cerr << "Machine Function " << "\n");
MF = &Fn;
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
MBB != MBBe; ++MBB)
AllocateBasicBlock(*MBB);
// add prologue we should preserve callee-save registers... // add prologue we should preserve callee-save registers...
MachineFunction::iterator Fi = Fn.begin(); MachineFunction::iterator Fi = Fn.begin();
@ -381,21 +389,22 @@ bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
MachineBasicBlock::iterator MBBi = MBB->begin(); MachineBasicBlock::iterator MBBi = MBB->begin();
RegInfo->emitPrologue(MBB, MBBi, NumBytesAllocated); RegInfo->emitPrologue(MBB, MBBi, NumBytesAllocated);
const MachineInstrInfo &MII = TM.getInstrInfo();
// add epilogue to restore the callee-save registers // add epilogue to restore the callee-save registers
// loop over the basic block // loop over the basic block
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
MBB != MBBe; ++MBB) MBB != MBBe; ++MBB) {
{
// check if last instruction is a RET // check if last instruction is a RET
MachineBasicBlock::iterator I = (*MBB).end(); MachineBasicBlock::iterator I = MBB->end();
MachineInstr *MI = *(--I); MachineInstr *MI = *--I;
const MachineInstrInfo &MII = TM.getInstrInfo();
if (MII.isReturn(MI->getOpcode())) { if (MII.isReturn(MI->getOpcode())) {
// this block has a return instruction, add epilogue // this block has a return instruction, add epilogue
RegInfo->emitEpilogue(MBB, I, NumBytesAllocated); RegInfo->emitEpilogue(MBB, I, NumBytesAllocated);
} }
} }
cleanupAfterFunction();
return false; // We never modify the LLVM itself. return false; // We never modify the LLVM itself.
} }