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[WinEH] Tweak funclet prologue/epilogue insertion to pass verifier
For some reason we'd never run MachineVerifier on WinEH code, and you explicitly have to ask for it with llc. I added it to a few test cases to get some coverage. Fixes PR25461. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252512 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -28,6 +28,7 @@
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/SetOperations.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Analysis/LibCallSemantics.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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#include "llvm/CodeGen/LiveVariables.h"
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@ -565,10 +566,12 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
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const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
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const BasicBlock *BB = MBB->getBasicBlock();
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const Function *Fn = MF->getFunction();
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if (LandingPadSuccs.size() > 1 &&
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!(AsmInfo &&
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AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj &&
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BB && isa<SwitchInst>(BB->getTerminator())))
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BB && isa<SwitchInst>(BB->getTerminator())) &&
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!isFuncletEHPersonality(classifyEHPersonality(Fn->getPersonalityFn())))
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report("MBB has more than one landing pad successor", MBB);
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// Call AnalyzeBranch. If it succeeds, there several more conditions to check.
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@ -722,6 +722,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF,
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addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MOVmr)), StackPtr, true, 16)
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.addReg(Establisher)
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.setMIFlag(MachineInstr::FrameSetup);
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MBB.addLiveIn(Establisher);
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}
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if (HasFP) {
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@ -787,9 +788,12 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF,
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}
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}
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// Mark the FramePtr as live-in in every block.
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
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I->addLiveIn(MachineFramePtr);
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// Mark the FramePtr as live-in in every block. Don't do this again for
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// funclet prologues.
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if (!IsFunclet) {
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for (MachineBasicBlock &EveryMBB : MF)
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EveryMBB.addLiveIn(MachineFramePtr);
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}
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} else {
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assert(!IsFunclet && "funclets without FPs not yet implemented");
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NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
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@ -1165,8 +1169,7 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
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.addReg(0);
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} else {
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// MOV32ri $TargetMBB, %eax
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BuildMI(MBB, FirstCSPop, DL, TII.get(X86::MOV32ri))
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.addReg(ReturnReg)
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BuildMI(MBB, FirstCSPop, DL, TII.get(X86::MOV32ri), ReturnReg)
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.addMBB(TargetMBB);
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}
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// Record that we've taken the address of TargetMBB and no longer just
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@ -1,5 +1,5 @@
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; RUN: llc < %s | FileCheck %s
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; RUN: llc -O0 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -O0 < %s | FileCheck %s
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target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-pc-windows-msvc"
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@ -1,5 +1,5 @@
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; RUN: llc -mtriple=i686-pc-windows-msvc < %s | FileCheck --check-prefix=X86 %s
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; RUN: llc -mtriple=x86_64-pc-windows-msvc < %s | FileCheck --check-prefix=X64 %s
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; RUN: llc -verify-machineinstrs -mtriple=i686-pc-windows-msvc < %s | FileCheck --check-prefix=X86 %s
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; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-windows-msvc < %s | FileCheck --check-prefix=X64 %s
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%rtti.TypeDescriptor2 = type { i8**, i8*, [3 x i8] }
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%eh.CatchableType = type { i32, i8*, i32, i32, i32, i32, i8* }
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@ -1,5 +1,5 @@
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; RUN: llc -mtriple=i686-pc-windows-msvc < %s | FileCheck --check-prefix=X86 %s
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; RUN: llc -mtriple=x86_64-pc-windows-msvc < %s | FileCheck --check-prefix=X64 %s
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; RUN: llc -verify-machineinstrs -mtriple=i686-pc-windows-msvc < %s | FileCheck --check-prefix=X86 %s
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; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-windows-msvc < %s | FileCheck --check-prefix=X64 %s
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; Loosely based on IR for this C++ source code:
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; void f(int p);
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@ -1,5 +1,5 @@
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; RUN: llc -mtriple=i686-pc-windows-msvc < %s | FileCheck --check-prefix=X86 %s
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; RUN: llc -mtriple=x86_64-pc-windows-msvc < %s | FileCheck --check-prefix=X64 %s
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; RUN: llc -verify-machineinstrs -mtriple=i686-pc-windows-msvc < %s | FileCheck --check-prefix=X86 %s
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; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-windows-msvc < %s | FileCheck --check-prefix=X64 %s
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%struct.Dtor = type { i8 }
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