RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-12-30 16:34:03 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Tighten operand checking on memory barrier instructions.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137176 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-08-09 23:25:42 +00:00
parent 77c714027c
commit c36481c474
5 changed files with 31 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
lib/Target/ARM/ARMInstrInfo.td
View File

@ -3814,6 +3814,7 @@ def MemBarrierOptOperand : AsmOperandClass {
def memb_opt : Operand<i32> { def memb_opt : Operand<i32> {
let PrintMethod = "printMemBOption"; let PrintMethod = "printMemBOption";
let ParserMatchClass = MemBarrierOptOperand; let ParserMatchClass = MemBarrierOptOperand;
let DecoderMethod = "DecodeMemBarrierOption";
} }
// memory barriers protect the atomic sequences // memory barriers protect the atomic sequences

26
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -131,6 +131,8 @@ static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Insn, static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
@ -2268,8 +2270,7 @@ static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
} }
unsigned imm = fieldFromInstruction32(Insn, 0, 4); unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Inst.addOperand(MCOperand::CreateImm(imm)); return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
return true;
} }
unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
@ -2347,3 +2348,24 @@ static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Val,
return true; return true;
} }
static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
switch (Val) {
default:
return false;
case 0xF: // SY
case 0xE: // ST
case 0xB: // ISH
case 0xA: // ISHST
case 0x7: // NSH
case 0x6: // NSHST
case 0x3: // OSH
case 0x2: // OSHST
break;
}
Inst.addOperand(MCOperand::CreateImm(Val));
return true;
}

5
test/MC/Disassembler/ARM/invalid-DMB-thumb.txt
View File

@ -1,12 +1,11 @@
# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} # RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}
# XFAIL: *
# Opcode=1908 Name=t2DMB Format=ARM_FORMAT_THUMBFRM(25) # Opcode=1908 Name=t2DMB Format=ARM_FORMAT_THUMBFRM(25)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 1| 0: 0: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 1| 0: 0: 0: 1| # | 1: 1: 1: 1| 0: 0: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 1| 0: 0: 0: 1|
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# #
# Inst{3-0} encodes the option: SY, ST, ISH, ISHST, NSH, NSHST, OSH, OSHST. # Inst{3-0} encodes the option: SY, ST, ISH, ISHST, NSH, NSHST, OSH, OSHST.
# Reject invalid encodings. # Reject invalid encodings.
# #

5
test/MC/Disassembler/ARM/invalid-DSB-arm.txt
View File

@ -1,12 +1,11 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
# XFAIL: *
# Opcode=102 Name=DSB Format=ARM_FORMAT_MISCFRM(26) # Opcode=102 Name=DSB Format=ARM_FORMAT_MISCFRM(26)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 1| 0: 1: 0: 1| 0: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 0: 0| # | 1: 1: 1: 1| 0: 1: 0: 1| 0: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 0: 0|
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# #
# Inst{3-0} encodes the option: SY, ST, ISH, ISHST, NSH, NSHST, OSH, OSHST. # Inst{3-0} encodes the option: SY, ST, ISH, ISHST, NSH, NSHST, OSH, OSHST.
# Reject invalid encodings. # Reject invalid encodings.
# #

5
test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt
View File

@ -1,12 +1,11 @@
# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} # RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}
# XFAIL: *
# Opcode=1894 Name=t2Bcc Format=ARM_FORMAT_THUMBFRM(25) # Opcode=1894 Name=t2Bcc Format=ARM_FORMAT_THUMBFRM(25)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 1| 0: 1: 1: 1| 1: 0: 1: 0| 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 1: 1| 0: 1: 0: 0| 0: 1: 0: 0| # | 1: 1: 1: 1| 0: 1: 1: 1| 1: 0: 1: 0| 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 1: 1| 0: 1: 0: 0| 0: 1: 0: 0|
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# #
# A8.6.16 B # A8.6.16 B
# if cond<3:1> == '111' then SEE "Related Encodings" # if cond<3:1> == '111' then SEE "Related Encodings"
0xaf 0xf7 0x44 0x8b 0xaf 0xf7 0x44 0x8b