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Back out some of recent register scavenger change by John Mosby. It broke a number of ARM tests.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78421 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-08-07 22:39:43 +00:00
parent 7116b7bb0c
commit c40f613034
1 changed files with 14 additions and 27 deletions
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33
lib/CodeGen/RegisterScavenging.cpp
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@ -99,13 +99,12 @@ void RegScavenger::initRegState() {
RegsAvailable ^= ReservedRegs; RegsAvailable ^= ReservedRegs;
// Live-in registers are in use. // Live-in registers are in use.
if (MBB) { if (!MBB || MBB->livein_empty())
if (!MBB->livein_empty()) return;
for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(), for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
E = MBB->livein_end(); I != E; ++I) E = MBB->livein_end(); I != E; ++I)
setUsed(*I); setUsed(*I);
} }
}
void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) { void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
MachineFunction &MF = *mbb->getParent(); MachineFunction &MF = *mbb->getParent();
@ -128,16 +127,9 @@ void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
// Create callee-saved registers bitvector. // Create callee-saved registers bitvector.
CalleeSavedRegs.resize(NumPhysRegs); CalleeSavedRegs.resize(NumPhysRegs);
const unsigned *CSRegs = TRI->getCalleeSavedRegs(); const unsigned *CSRegs = TRI->getCalleeSavedRegs();
if (CSRegs != NULL) { if (CSRegs != NULL)
// At this point we know which CSRs are used by the current function, for (unsigned i = 0; CSRegs[i]; ++i)
// so allow those that are _not_ already used to be available to RS. CalleeSavedRegs.set(CSRegs[i]);
MachineFrameInfo *FFI = MF.getFrameInfo();
const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
CalleeSavedRegs.set(CSI[i].getReg());
}
}
} }
// RS used within emit{Pro,Epi}logue() // RS used within emit{Pro,Epi}logue()
@ -217,11 +209,6 @@ void RegScavenger::forward() {
ScavengeRestore = NULL; ScavengeRestore = NULL;
} }
#if 0
if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
return;
#endif
// Separate register operands into 3 classes: uses, defs, earlyclobbers. // Separate register operands into 3 classes: uses, defs, earlyclobbers.
SmallVector<std::pair<const MachineOperand*,unsigned>, 4> UseMOs; SmallVector<std::pair<const MachineOperand*,unsigned>, 4> UseMOs;
SmallVector<std::pair<const MachineOperand*,unsigned>, 4> DefMOs; SmallVector<std::pair<const MachineOperand*,unsigned>, 4> DefMOs;
@ -234,9 +221,11 @@ void RegScavenger::forward() {
UseMOs.push_back(std::make_pair(&MO,i)); UseMOs.push_back(std::make_pair(&MO,i));
else if (MO.isEarlyClobber()) else if (MO.isEarlyClobber())
EarlyClobberMOs.push_back(std::make_pair(&MO,i)); EarlyClobberMOs.push_back(std::make_pair(&MO,i));
else if (MO.isDef()) else {
assert(MO.isDef());
DefMOs.push_back(std::make_pair(&MO,i)); DefMOs.push_back(std::make_pair(&MO,i));
} }
}
// Process uses first. // Process uses first.
BitVector KillRegs(NumPhysRegs); BitVector KillRegs(NumPhysRegs);
@ -245,9 +234,7 @@ void RegScavenger::forward() {
unsigned Idx = UseMOs[i].second; unsigned Idx = UseMOs[i].second;
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
// Allow free CSRs to be processed as uses. assert(isUsed(Reg) && "Using an undefined register!");
assert((isUsed(Reg) || !CalleeSavedRegs[Reg]) &&
"Using an undefined register!");
// Two-address operands implicitly kill. // Two-address operands implicitly kill.
if ((MO.isKill() || MI->isRegTiedToDefOperand(Idx)) && !isReserved(Reg)) { if ((MO.isKill() || MI->isRegTiedToDefOperand(Idx)) && !isReserved(Reg)) {
@ -440,7 +427,7 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
? MachineBasicBlock::iterator(MaxUseMI) : MBB->getFirstTerminator(); ? MachineBasicBlock::iterator(MaxUseMI) : MBB->getFirstTerminator();
TII->loadRegFromStackSlot(*MBB, II, SReg, ScavengingFrameIndex, RC); TII->loadRegFromStackSlot(*MBB, II, SReg, ScavengingFrameIndex, RC);
ScavengeRestore = prior(II); ScavengeRestore = prior(II);
// Doing this here leads to infinite regress // Doing this here leads to infinite regress.
// ScavengedReg = SReg; // ScavengedReg = SReg;
ScavengedRC = RC; ScavengedRC = RC;