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Emit <regmask R1 R2 R3 ...> instead of just <regmask> in IR dumps.

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Reviewers: qcolombet

Subscribers: kparzysz, qcolombet, llvm-commits

Differential Revision: http://reviews.llvm.org/D11644

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245433 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2015-08-19 12:03:04 +00:00
parent ab30763357
commit c457f1e27b
1 changed files with 25 additions and 2 deletions
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27
lib/CodeGen/MachineInstr.cpp
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@ -33,6 +33,7 @@
#include "llvm/IR/Value.h" #include "llvm/IR/Value.h"
#include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCSymbol.h" #include "llvm/MC/MCSymbol.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h" #include "llvm/Support/MathExtras.h"
@ -43,6 +44,11 @@
#include "llvm/Target/TargetSubtargetInfo.h" #include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm; using namespace llvm;
static cl::opt<bool> PrintWholeRegMask(
"print-whole-regmask",
cl::desc("Print the full contents of regmask operands in IR dumps"),
cl::init(true), cl::Hidden);
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// MachineOperand Implementation // MachineOperand Implementation
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@ -407,9 +413,26 @@ void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
if (getOffset()) OS << "+" << getOffset(); if (getOffset()) OS << "+" << getOffset();
OS << '>'; OS << '>';
break; break;
case MachineOperand::MO_RegisterMask: case MachineOperand::MO_RegisterMask: {
OS << "<regmask>"; unsigned NumRegsInMask = 0;
unsigned NumRegsEmitted = 0;
OS << "<regmask";
for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
unsigned MaskWord = i / 32;
unsigned MaskBit = i % 32;
if (getRegMask()[MaskWord] & (1 << MaskBit)) {
if (PrintWholeRegMask || NumRegsEmitted <= 10) {
OS << " " << PrintReg(i, TRI);
NumRegsEmitted++;
}
NumRegsInMask++;
}
}
if (NumRegsEmitted != NumRegsInMask)
OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
OS << ">";
break; break;
}
case MachineOperand::MO_RegisterLiveOut: case MachineOperand::MO_RegisterLiveOut:
OS << "<regliveout>"; OS << "<regliveout>";
break; break;