From c5409a6b1ce47b995aa2d8718d2d8b8ae1ed36a6 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Fri, 3 Jun 2016 10:15:36 +0000 Subject: [PATCH] [X86] Regenerated nontemporal store tests and added tests for all 128-bit vector types git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271651 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/nontemporal.ll | 137 +++++++++++++++++++++++++++++--- 1 file changed, 124 insertions(+), 13 deletions(-) diff --git a/test/CodeGen/X86/nontemporal.ll b/test/CodeGen/X86/nontemporal.ll index 9a2f23596f7..33d5caba597 100644 --- a/test/CodeGen/X86/nontemporal.ll +++ b/test/CodeGen/X86/nontemporal.ll @@ -1,24 +1,135 @@ -; RUN: llc < %s -mtriple x86_64-unknown-unknown | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32-SSE +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X32-AVX +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64-SSE +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X64-AVX -define void @f(<4 x float> %A, i8* %B, <2 x double> %C, i32 %D, <2 x i64> %E, i64 %F) { -; CHECK: movntps +define void @f(<4 x float> %A, i8* %B, <2 x double> %C, i32 %D, <2 x i64> %E, <4 x i32> %F, <8 x i16> %G, <16 x i8> %H, i64 %I) nounwind { +; X32-SSE-LABEL: f: +; X32-SSE: # BB#0: +; X32-SSE-NEXT: pushl %ebp +; X32-SSE-NEXT: movl %esp, %ebp +; X32-SSE-NEXT: pushl %esi +; X32-SSE-NEXT: andl $-16, %esp +; X32-SSE-NEXT: subl $16, %esp +; X32-SSE-NEXT: movl 72(%ebp), %eax +; X32-SSE-NEXT: movl 76(%ebp), %ecx +; X32-SSE-NEXT: movl 12(%ebp), %edx +; X32-SSE-NEXT: movdqa 56(%ebp), %xmm3 +; X32-SSE-NEXT: movdqa 40(%ebp), %xmm4 +; X32-SSE-NEXT: movdqa 24(%ebp), %xmm5 +; X32-SSE-NEXT: movl 8(%ebp), %esi +; X32-SSE-NEXT: addps .LCPI0_0, %xmm0 +; X32-SSE-NEXT: movntps %xmm0, (%esi) +; X32-SSE-NEXT: paddq .LCPI0_1, %xmm2 +; X32-SSE-NEXT: movntdq %xmm2, (%esi) +; X32-SSE-NEXT: addpd .LCPI0_2, %xmm1 +; X32-SSE-NEXT: movntpd %xmm1, (%esi) +; X32-SSE-NEXT: paddd .LCPI0_3, %xmm5 +; X32-SSE-NEXT: movntdq %xmm5, (%esi) +; X32-SSE-NEXT: paddw .LCPI0_4, %xmm4 +; X32-SSE-NEXT: movntdq %xmm4, (%esi) +; X32-SSE-NEXT: paddb .LCPI0_5, %xmm3 +; X32-SSE-NEXT: movntdq %xmm3, (%esi) +; X32-SSE-NEXT: movntil %edx, (%esi) +; X32-SSE-NEXT: movntil %ecx, 4(%esi) +; X32-SSE-NEXT: movntil %eax, (%esi) +; X32-SSE-NEXT: leal -4(%ebp), %esp +; X32-SSE-NEXT: popl %esi +; X32-SSE-NEXT: popl %ebp +; X32-SSE-NEXT: retl +; +; X32-AVX-LABEL: f: +; X32-AVX: # BB#0: +; X32-AVX-NEXT: pushl %ebp +; X32-AVX-NEXT: movl %esp, %ebp +; X32-AVX-NEXT: pushl %esi +; X32-AVX-NEXT: andl $-16, %esp +; X32-AVX-NEXT: subl $16, %esp +; X32-AVX-NEXT: movl 72(%ebp), %eax +; X32-AVX-NEXT: movl 76(%ebp), %ecx +; X32-AVX-NEXT: movl 12(%ebp), %edx +; X32-AVX-NEXT: vmovdqa 56(%ebp), %xmm3 +; X32-AVX-NEXT: vmovdqa 40(%ebp), %xmm4 +; X32-AVX-NEXT: vmovdqa 24(%ebp), %xmm5 +; X32-AVX-NEXT: movl 8(%ebp), %esi +; X32-AVX-NEXT: vaddps .LCPI0_0, %xmm0, %xmm0 +; X32-AVX-NEXT: vmovntps %xmm0, (%esi) +; X32-AVX-NEXT: vpaddq .LCPI0_1, %xmm2, %xmm0 +; X32-AVX-NEXT: vmovntdq %xmm0, (%esi) +; X32-AVX-NEXT: vaddpd .LCPI0_2, %xmm1, %xmm0 +; X32-AVX-NEXT: vmovntpd %xmm0, (%esi) +; X32-AVX-NEXT: vpaddd .LCPI0_3, %xmm5, %xmm0 +; X32-AVX-NEXT: vmovntdq %xmm0, (%esi) +; X32-AVX-NEXT: vpaddw .LCPI0_4, %xmm4, %xmm0 +; X32-AVX-NEXT: vmovntdq %xmm0, (%esi) +; X32-AVX-NEXT: vpaddb .LCPI0_5, %xmm3, %xmm0 +; X32-AVX-NEXT: vmovntdq %xmm0, (%esi) +; X32-AVX-NEXT: movntil %edx, (%esi) +; X32-AVX-NEXT: movntil %ecx, 4(%esi) +; X32-AVX-NEXT: movntil %eax, (%esi) +; X32-AVX-NEXT: leal -4(%ebp), %esp +; X32-AVX-NEXT: popl %esi +; X32-AVX-NEXT: popl %ebp +; X32-AVX-NEXT: retl +; +; X64-SSE-LABEL: f: +; X64-SSE: # BB#0: +; X64-SSE-NEXT: addps {{.*}}(%rip), %xmm0 +; X64-SSE-NEXT: movntps %xmm0, (%rdi) +; X64-SSE-NEXT: paddq {{.*}}(%rip), %xmm2 +; X64-SSE-NEXT: movntdq %xmm2, (%rdi) +; X64-SSE-NEXT: addpd {{.*}}(%rip), %xmm1 +; X64-SSE-NEXT: movntpd %xmm1, (%rdi) +; X64-SSE-NEXT: paddd {{.*}}(%rip), %xmm3 +; X64-SSE-NEXT: movntdq %xmm3, (%rdi) +; X64-SSE-NEXT: paddw {{.*}}(%rip), %xmm4 +; X64-SSE-NEXT: movntdq %xmm4, (%rdi) +; X64-SSE-NEXT: paddb {{.*}}(%rip), %xmm5 +; X64-SSE-NEXT: movntdq %xmm5, (%rdi) +; X64-SSE-NEXT: movntil %esi, (%rdi) +; X64-SSE-NEXT: movntiq %rdx, (%rdi) +; X64-SSE-NEXT: retq +; +; X64-AVX-LABEL: f: +; X64-AVX: # BB#0: +; X64-AVX-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0 +; X64-AVX-NEXT: vmovntps %xmm0, (%rdi) +; X64-AVX-NEXT: vpaddq {{.*}}(%rip), %xmm2, %xmm0 +; X64-AVX-NEXT: vmovntdq %xmm0, (%rdi) +; X64-AVX-NEXT: vaddpd {{.*}}(%rip), %xmm1, %xmm0 +; X64-AVX-NEXT: vmovntpd %xmm0, (%rdi) +; X64-AVX-NEXT: vpaddd {{.*}}(%rip), %xmm3, %xmm0 +; X64-AVX-NEXT: vmovntdq %xmm0, (%rdi) +; X64-AVX-NEXT: vpaddw {{.*}}(%rip), %xmm4, %xmm0 +; X64-AVX-NEXT: vmovntdq %xmm0, (%rdi) +; X64-AVX-NEXT: vpaddb {{.*}}(%rip), %xmm5, %xmm0 +; X64-AVX-NEXT: vmovntdq %xmm0, (%rdi) +; X64-AVX-NEXT: movntil %esi, (%rdi) +; X64-AVX-NEXT: movntiq %rdx, (%rdi) +; X64-AVX-NEXT: retq %cast = bitcast i8* %B to <4 x float>* - %A2 = fadd <4 x float> %A, + %A2 = fadd <4 x float> %A, store <4 x float> %A2, <4 x float>* %cast, align 16, !nontemporal !0 -; CHECK: movntdq %cast1 = bitcast i8* %B to <2 x i64>* %E2 = add <2 x i64> %E, store <2 x i64> %E2, <2 x i64>* %cast1, align 16, !nontemporal !0 -; CHECK: movntpd %cast2 = bitcast i8* %B to <2 x double>* - %C2 = fadd <2 x double> %C, + %C2 = fadd <2 x double> %C, store <2 x double> %C2, <2 x double>* %cast2, align 16, !nontemporal !0 -; CHECK: movntil - %cast3 = bitcast i8* %B to i32* - store i32 %D, i32* %cast3, align 1, !nontemporal !0 -; CHECK: movntiq - %cast4 = bitcast i8* %B to i64* - store i64 %F, i64* %cast4, align 1, !nontemporal !0 + %cast3 = bitcast i8* %B to <4 x i32>* + %F2 = add <4 x i32> %F, + store <4 x i32> %F2, <4 x i32>* %cast3, align 16, !nontemporal !0 + %cast4 = bitcast i8* %B to <8 x i16>* + %G2 = add <8 x i16> %G, + store <8 x i16> %G2, <8 x i16>* %cast4, align 16, !nontemporal !0 + %cast5 = bitcast i8* %B to <16 x i8>* + %H2 = add <16 x i8> %H, + store <16 x i8> %H2, <16 x i8>* %cast5, align 16, !nontemporal !0 + %cast6 = bitcast i8* %B to i32* + store i32 %D, i32* %cast6, align 1, !nontemporal !0 + %cast7 = bitcast i8* %B to i64* + store i64 %I, i64* %cast7, align 1, !nontemporal !0 ret void }