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Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)

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instructions with writebacks. And add test a case for all opcodes handed by
DecodeVLD2DupInstruction() in ARMDisassembler.cpp .


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154884 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Enderby 2012-04-17 00:49:27 +00:00
parent 8975f510c0
commit c5a2a33938
3 changed files with 76 additions and 7 deletions
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8
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -2690,7 +2690,6 @@ static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
unsigned align = fieldFromInstruction32(Insn, 4, 1);
unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
unsigned pred = fieldFromInstruction32(Insn, 22, 4);
align *= 2*size;
switch (Inst.getOpcode()) {
@ -2721,16 +2720,11 @@ static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(align));
if (Rm == 0xD)
Inst.addOperand(MCOperand::CreateReg(0));
else if (Rm != 0xF) {
if (Rm != 0xD && Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
}
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
return MCDisassembler::Fail;
return S;
}

37
test/MC/Disassembler/ARM/neon.txt
View File

@ -2243,3 +2243,40 @@
# CHECK: vld4.16 {d8, d10, d12, d14}, [r4]
0x8f 0x81 0x24 0xf4
# CHECK: vld4.32 {d8, d10, d12, d14}, [r4]
# rdar://11256967
0x0f 0x0d 0xa2 0xf4
# CHECK: vld2.8 {d0[], d1[]}, [r2]
0x4f 0x0d 0xa2 0xf4
# CHECK: vld2.16 {d0[], d1[]}, [r2]
0x8f 0x0d 0xa2 0xf4
# CHECK: vld2.32 {d0[], d1[]}, [r2]
0x0d 0x0d 0xa2 0xf4
# CHECK: vld2.8 {d0[], d1[]}, [r2]!
0x4d 0x0d 0xa2 0xf4
# CHECK: vld2.16 {d0[], d1[]}, [r2]!
0x8d 0x0d 0xa2 0xf4
# CHECK: vld2.32 {d0[], d1[]}, [r2]!
0x03 0x0d 0xa2 0xf4
# CHECK: vld2.8 {d0[], d1[]}, [r2], r3
0x43 0x0d 0xa2 0xf4
# CHECK: vld2.16 {d0[], d1[]}, [r2], r3
0x83 0x0d 0xa2 0xf4
# CHECK: vld2.32 {d0[], d1[]}, [r2], r3
0x2f 0x0d 0xa3 0xf4
# CHECK: vld2.8 {d0[], d2[]}, [r3]
0x6f 0x0d 0xa3 0xf4
# CHECK: vld2.16 {d0[], d2[]}, [r3]
0xaf 0x0d 0xa3 0xf4
# CHECK: vld2.32 {d0[], d2[]}, [r3]
0x2d 0x0d 0xa3 0xf4
# CHECK: vld2.8 {d0[], d2[]}, [r3]!
0x6d 0x0d 0xa3 0xf4
# CHECK: vld2.16 {d0[], d2[]}, [r3]!
0xad 0x0d 0xa3 0xf4
# CHECK: vld2.32 {d0[], d2[]}, [r3]!
0x24 0x0d 0xa3 0xf4
# CHECK: vld2.8 {d0[], d2[]}, [r3], r4
0x64 0x0d 0xa3 0xf4
0xa4 0x0d 0xa3 0xf4
# CHECK: vld2.32 {d0[], d2[]}, [r3], r4

38
test/MC/Disassembler/ARM/neont2.txt
View File

@ -1960,3 +1960,41 @@
# CHECK: vld4.16 {d8, d10, d12, d14}, [r4]
0x24 0xf9 0x8f 0x81
# CHECK: vld4.32 {d8, d10, d12, d14}, [r4]
# rdar://11256967
0xa2 0xf9 0x0f 0x0d
# CHECK: vld2.8 {d0[], d1[]}, [r2]
0xa2 0xf9 0x4f 0x0d
# CHECK: vld2.16 {d0[], d1[]}, [r2]
0xa2 0xf9 0x8f 0x0d
# CHECK: vld2.32 {d0[], d1[]}, [r2]
0xa2 0xf9 0x0d 0x0d
# CHECK: vld2.8 {d0[], d1[]}, [r2]!
0xa2 0xf9 0x4d 0x0d
# CHECK: vld2.16 {d0[], d1[]}, [r2]!
0xa2 0xf9 0x8d 0x0d
# CHECK: vld2.32 {d0[], d1[]}, [r2]!
0xa2 0xf9 0x03 0x0d
# CHECK: vld2.8 {d0[], d1[]}, [r2], r3
0xa2 0xf9 0x43 0x0d
# CHECK: vld2.16 {d0[], d1[]}, [r2], r3
0xa2 0xf9 0x83 0x0d
# CHECK: vld2.32 {d0[], d1[]}, [r2], r3
0xa3 0xf9 0x2f 0x0d
# CHECK: vld2.8 {d0[], d2[]}, [r3]
0xa3 0xf9 0x6f 0x0d
# CHECK: vld2.16 {d0[], d2[]}, [r3]
0xa3 0xf9 0xaf 0x0d
# CHECK: vld2.32 {d0[], d2[]}, [r3]
0xa3 0xf9 0x2d 0x0d
# CHECK: vld2.8 {d0[], d2[]}, [r3]!
0xa3 0xf9 0x6d 0x0d
# CHECK: vld2.16 {d0[], d2[]}, [r3]!
0xa3 0xf9 0xad 0x0d
# CHECK: vld2.32 {d0[], d2[]}, [r3]!
0xa3 0xf9 0x24 0x0d
# CHECK: vld2.8 {d0[], d2[]}, [r3], r4
0xa3 0xf9 0x64 0x0d
# CHECK: vld2.16 {d0[], d2[]}, [r3], r4
0xa3 0xf9 0xa4 0x0d
# CHECK: vld2.32 {d0[], d2[]}, [r3], r4