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Renamed files to have the `X86' prefix for uniqueness purposes.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15238 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2004-07-26 18:43:11 +00:00
parent b097f216b0
commit c6d398abbb
5 changed files with 0 additions and 6300 deletions
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lib/Target/X86/FloatingPoint.cpp
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//===-- FloatingPoint.cpp - Floating point Reg -> Stack converter ---------===//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines the pass which converts floating point instructions from
// virtual registers into register stack instructions. This pass uses live
// variable information to indicate where the FPn registers are used and their
// lifetimes.
//
// This pass is hampered by the lack of decent CFG manipulation routines for
// machine code. In particular, this wants to be able to split critical edges
// as necessary, traverse the machine basic block CFG in depth-first order, and
// allow there to be multiple machine basic blocks for each LLVM basicblock
// (needed for critical edge splitting).
//
// In particular, this pass currently barfs on critical edges. Because of this,
// it requires the instruction selector to insert FP_REG_KILL instructions on
// the exits of any basic block that has critical edges going from it, or which
// branch to a critical basic block.
//
// FIXME: this is not implemented yet. The stackifier pass only works on local
// basic blocks.
//
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "fp"
#include "X86.h"
#include "X86InstrInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "Support/Debug.h"
#include "Support/DepthFirstIterator.h"
#include "Support/Statistic.h"
#include "Support/STLExtras.h"
#include <algorithm>
#include <set>
using namespace llvm;
namespace {
Statistic<> NumFXCH("x86-codegen", "Number of fxch instructions inserted");
Statistic<> NumFP ("x86-codegen", "Number of floating point instructions");
struct FPS : public MachineFunctionPass {
virtual bool runOnMachineFunction(MachineFunction &MF);
virtual const char *getPassName() const { return "X86 FP Stackifier"; }
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<LiveVariables>();
MachineFunctionPass::getAnalysisUsage(AU);
}
private:
LiveVariables *LV; // Live variable info for current function...
MachineBasicBlock *MBB; // Current basic block
unsigned Stack[8]; // FP<n> Registers in each stack slot...
unsigned RegMap[8]; // Track which stack slot contains each register
unsigned StackTop; // The current top of the FP stack.
void dumpStack() const {
std::cerr << "Stack contents:";
for (unsigned i = 0; i != StackTop; ++i) {
std::cerr << " FP" << Stack[i];
assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
}
std::cerr << "\n";
}
private:
// getSlot - Return the stack slot number a particular register number is
// in...
unsigned getSlot(unsigned RegNo) const {
assert(RegNo < 8 && "Regno out of range!");
return RegMap[RegNo];
}
// getStackEntry - Return the X86::FP<n> register in register ST(i)
unsigned getStackEntry(unsigned STi) const {
assert(STi < StackTop && "Access past stack top!");
return Stack[StackTop-1-STi];
}
// getSTReg - Return the X86::ST(i) register which contains the specified
// FP<RegNo> register
unsigned getSTReg(unsigned RegNo) const {
return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0;
}
// pushReg - Push the specified FP<n> register onto the stack
void pushReg(unsigned Reg) {
assert(Reg < 8 && "Register number out of range!");
assert(StackTop < 8 && "Stack overflow!");
Stack[StackTop] = Reg;
RegMap[Reg] = StackTop++;
}
bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) {
if (!isAtTop(RegNo)) {
unsigned Slot = getSlot(RegNo);
unsigned STReg = getSTReg(RegNo);
unsigned RegOnTop = getStackEntry(0);
// Swap the slots the regs are in
std::swap(RegMap[RegNo], RegMap[RegOnTop]);
// Swap stack slot contents
assert(RegMap[RegOnTop] < StackTop);
std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
// Emit an fxch to update the runtime processors version of the state
BuildMI(*MBB, I, X86::FXCH, 1).addReg(STReg);
NumFXCH++;
}
}
void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
unsigned STReg = getSTReg(RegNo);
pushReg(AsReg); // New register on top of stack
BuildMI(*MBB, I, X86::FLDrr, 1).addReg(STReg);
}
// popStackAfter - Pop the current value off of the top of the FP stack
// after the specified instruction.
void popStackAfter(MachineBasicBlock::iterator &I);
// freeStackSlotAfter - Free the specified register from the register stack,
// so that it is no longer in a register. If the register is currently at
// the top of the stack, we just pop the current instruction, otherwise we
// store the current top-of-stack into the specified slot, then pop the top
// of stack.
void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
void handleZeroArgFP(MachineBasicBlock::iterator &I);
void handleOneArgFP(MachineBasicBlock::iterator &I);
void handleOneArgFPRW(MachineBasicBlock::iterator &I);
void handleTwoArgFP(MachineBasicBlock::iterator &I);
void handleCompareFP(MachineBasicBlock::iterator &I);
void handleCondMovFP(MachineBasicBlock::iterator &I);
void handleSpecialFP(MachineBasicBlock::iterator &I);
};
}
FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
/// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
/// register references into FP stack references.
///
bool FPS::runOnMachineFunction(MachineFunction &MF) {
LV = &getAnalysis<LiveVariables>();
StackTop = 0;
// Process the function in depth first order so that we process at least one
// of the predecessors for every reachable block in the function.
std::set<MachineBasicBlock*> Processed;
MachineBasicBlock *Entry = MF.begin();
bool Changed = false;
for (df_ext_iterator<MachineBasicBlock*, std::set<MachineBasicBlock*> >
I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed);
I != E; ++I)
Changed |= processBasicBlock(MF, **I);
return Changed;
}
/// processBasicBlock - Loop over all of the instructions in the basic block,
/// transforming FP instructions into their stack form.
///
bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
bool Changed = false;
MBB = &BB;
for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
MachineInstr *MI = I;
unsigned Flags = TII.get(MI->getOpcode()).TSFlags;
if ((Flags & X86II::FPTypeMask) == X86II::NotFP)
continue; // Efficiently ignore non-fp insts!
MachineInstr *PrevMI = 0;
if (I != BB.begin())
PrevMI = prior(I);
++NumFP; // Keep track of # of pseudo instrs
DEBUG(std::cerr << "\nFPInst:\t";
MI->print(std::cerr, &(MF.getTarget())));
// Get dead variables list now because the MI pointer may be deleted as part
// of processing!
LiveVariables::killed_iterator IB = LV->dead_begin(MI);
LiveVariables::killed_iterator IE = LV->dead_end(MI);
DEBUG(const MRegisterInfo *MRI = MF.getTarget().getRegisterInfo();
LiveVariables::killed_iterator I = LV->killed_begin(MI);
LiveVariables::killed_iterator E = LV->killed_end(MI);
if (I != E) {
std::cerr << "Killed Operands:";
for (; I != E; ++I)
std::cerr << " %" << MRI->getName(I->second);
std::cerr << "\n";
});
switch (Flags & X86II::FPTypeMask) {
case X86II::ZeroArgFP: handleZeroArgFP(I); break;
case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0)
case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
case X86II::TwoArgFP: handleTwoArgFP(I); break;
case X86II::CompareFP: handleCompareFP(I); break;
case X86II::CondMovFP: handleCondMovFP(I); break;
case X86II::SpecialFP: handleSpecialFP(I); break;
default: assert(0 && "Unknown FP Type!");
}
// Check to see if any of the values defined by this instruction are dead
// after definition. If so, pop them.
for (; IB != IE; ++IB) {
unsigned Reg = IB->second;
if (Reg >= X86::FP0 && Reg <= X86::FP6) {
DEBUG(std::cerr << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
freeStackSlotAfter(I, Reg-X86::FP0);
}
}
// Print out all of the instructions expanded to if -debug
DEBUG(
MachineBasicBlock::iterator PrevI(PrevMI);
if (I == PrevI) {
std::cerr << "Just deleted pseudo instruction\n";
} else {
MachineBasicBlock::iterator Start = I;
// Rewind to first instruction newly inserted.
while (Start != BB.begin() && prior(Start) != PrevI) --Start;
std::cerr << "Inserted instructions:\n\t";
Start->print(std::cerr, &MF.getTarget());
while (++Start != next(I));
}
dumpStack();
);
Changed = true;
}
assert(StackTop == 0 && "Stack not empty at end of basic block?");
return Changed;
}
//===----------------------------------------------------------------------===//
// Efficient Lookup Table Support
//===----------------------------------------------------------------------===//
namespace {
struct TableEntry {
unsigned from;
unsigned to;
bool operator<(const TableEntry &TE) const { return from < TE.from; }
bool operator<(unsigned V) const { return from < V; }
};
}
static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
for (unsigned i = 0; i != NumEntries-1; ++i)
if (!(Table[i] < Table[i+1])) return false;
return true;
}
static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
if (I != Table+N && I->from == Opcode)
return I->to;
return -1;
}
#define ARRAY_SIZE(TABLE) \
(sizeof(TABLE)/sizeof(TABLE[0]))
#ifdef NDEBUG
#define ASSERT_SORTED(TABLE)
#else
#define ASSERT_SORTED(TABLE) \
{ static bool TABLE##Checked = false; \
if (!TABLE##Checked) \
assert(TableIsSorted(TABLE, ARRAY_SIZE(TABLE)) && \
"All lookup tables must be sorted for efficient access!"); \
}
#endif
//===----------------------------------------------------------------------===//
// Helper Methods
//===----------------------------------------------------------------------===//
// PopTable - Sorted map of instructions to their popping version. The first
// element is an instruction, the second is the version which pops.
//
static const TableEntry PopTable[] = {
{ X86::FADDrST0 , X86::FADDPrST0 },
{ X86::FDIVRrST0, X86::FDIVRPrST0 },
{ X86::FDIVrST0 , X86::FDIVPrST0 },
{ X86::FIST16m , X86::FISTP16m },
{ X86::FIST32m , X86::FISTP32m },
{ X86::FMULrST0 , X86::FMULPrST0 },
{ X86::FST32m , X86::FSTP32m },
{ X86::FST64m , X86::FSTP64m },
{ X86::FSTrr , X86::FSTPrr },
{ X86::FSUBRrST0, X86::FSUBRPrST0 },
{ X86::FSUBrST0 , X86::FSUBPrST0 },
{ X86::FUCOMIr , X86::FUCOMIPr },
{ X86::FUCOMPr , X86::FUCOMPPr },
{ X86::FUCOMr , X86::FUCOMPr },
};
/// popStackAfter - Pop the current value off of the top of the FP stack after
/// the specified instruction. This attempts to be sneaky and combine the pop
/// into the instruction itself if possible. The iterator is left pointing to
/// the last instruction, be it a new pop instruction inserted, or the old
/// instruction if it was modified in place.
///
void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
ASSERT_SORTED(PopTable);
assert(StackTop > 0 && "Cannot pop empty stack!");
RegMap[Stack[--StackTop]] = ~0; // Update state
// Check to see if there is a popping version of this instruction...
int Opcode = Lookup(PopTable, ARRAY_SIZE(PopTable), I->getOpcode());
if (Opcode != -1) {
I->setOpcode(Opcode);
if (Opcode == X86::FUCOMPPr)
I->RemoveOperand(0);
} else { // Insert an explicit pop
I = BuildMI(*MBB, ++I, X86::FSTPrr, 1).addReg(X86::ST0);
}
}
/// freeStackSlotAfter - Free the specified register from the register stack, so
/// that it is no longer in a register. If the register is currently at the top
/// of the stack, we just pop the current instruction, otherwise we store the
/// current top-of-stack into the specified slot, then pop the top of stack.
void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy.
popStackAfter(I);
return;
}
// Otherwise, store the top of stack into the dead slot, killing the operand
// without having to add in an explicit xchg then pop.
//
unsigned STReg = getSTReg(FPRegNo);
unsigned OldSlot = getSlot(FPRegNo);
unsigned TopReg = Stack[StackTop-1];
Stack[OldSlot] = TopReg;
RegMap[TopReg] = OldSlot;
RegMap[FPRegNo] = ~0;
Stack[--StackTop] = ~0;
I = BuildMI(*MBB, ++I, X86::FSTPrr, 1).addReg(STReg);
}
static unsigned getFPReg(const MachineOperand &MO) {
assert(MO.isRegister() && "Expected an FP register!");
unsigned Reg = MO.getReg();
assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
return Reg - X86::FP0;
}
//===----------------------------------------------------------------------===//
// Instruction transformation implementation
//===----------------------------------------------------------------------===//
/// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
///
void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
unsigned DestReg = getFPReg(MI->getOperand(0));
MI->RemoveOperand(0); // Remove the explicit ST(0) operand
// Result gets pushed on the stack...
pushReg(DestReg);
}
/// handleOneArgFP - fst <mem>, ST(0)
///
void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
assert((MI->getNumOperands() == 5 || MI->getNumOperands() == 1) &&
"Can only handle fst* & ftst instructions!");
// Is this the last use of the source register?
unsigned Reg = getFPReg(MI->getOperand(MI->getNumOperands()-1));
bool KillsSrc = false;
for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
E = LV->killed_end(MI); KI != E; ++KI)
KillsSrc |= KI->second == X86::FP0+Reg;
// FSTP80r and FISTP64r are strange because there are no non-popping versions.
// If we have one _and_ we don't want to pop the operand, duplicate the value
// on the stack instead of moving it. This ensure that popping the value is
// always ok.
//
if ((MI->getOpcode() == X86::FSTP80m ||
MI->getOpcode() == X86::FISTP64m) && !KillsSrc) {
duplicateToTop(Reg, 7 /*temp register*/, I);
} else {
moveToTop(Reg, I); // Move to the top of the stack...
}
MI->RemoveOperand(MI->getNumOperands()-1); // Remove explicit ST(0) operand
if (MI->getOpcode() == X86::FSTP80m || MI->getOpcode() == X86::FISTP64m) {
assert(StackTop > 0 && "Stack empty??");
--StackTop;
} else if (KillsSrc) { // Last use of operand?
popStackAfter(I);
}
}
/// handleOneArgFPRW: Handle instructions that read from the top of stack and
/// replace the value with a newly computed value. These instructions may have
/// non-fp operands after their FP operands.
///
/// Examples:
/// R1 = fchs R2
/// R1 = fadd R2, [mem]
///
void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
assert(MI->getNumOperands() >= 2 && "FPRW instructions must have 2 ops!!");
// Is this the last use of the source register?
unsigned Reg = getFPReg(MI->getOperand(1));
bool KillsSrc = false;
for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
E = LV->killed_end(MI); KI != E; ++KI)
KillsSrc |= KI->second == X86::FP0+Reg;
if (KillsSrc) {
// If this is the last use of the source register, just make sure it's on
// the top of the stack.
moveToTop(Reg, I);
assert(StackTop > 0 && "Stack cannot be empty!");
--StackTop;
pushReg(getFPReg(MI->getOperand(0)));
} else {
// If this is not the last use of the source register, _copy_ it to the top
// of the stack.
duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
}
MI->RemoveOperand(1); // Drop the source operand.
MI->RemoveOperand(0); // Drop the destination operand.
}
//===----------------------------------------------------------------------===//
// Define tables of various ways to map pseudo instructions
//
// ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i)
static const TableEntry ForwardST0Table[] = {
{ X86::FpADD , X86::FADDST0r },
{ X86::FpDIV , X86::FDIVST0r },
{ X86::FpMUL , X86::FMULST0r },
{ X86::FpSUB , X86::FSUBST0r },
};
// ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0)
static const TableEntry ReverseST0Table[] = {
{ X86::FpADD , X86::FADDST0r }, // commutative
{ X86::FpDIV , X86::FDIVRST0r },
{ X86::FpMUL , X86::FMULST0r }, // commutative
{ X86::FpSUB , X86::FSUBRST0r },
};
// ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i)
static const TableEntry ForwardSTiTable[] = {
{ X86::FpADD , X86::FADDrST0 }, // commutative
{ X86::FpDIV , X86::FDIVRrST0 },
{ X86::FpMUL , X86::FMULrST0 }, // commutative
{ X86::FpSUB , X86::FSUBRrST0 },
};
// ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0)
static const TableEntry ReverseSTiTable[] = {
{ X86::FpADD , X86::FADDrST0 },
{ X86::FpDIV , X86::FDIVrST0 },
{ X86::FpMUL , X86::FMULrST0 },
{ X86::FpSUB , X86::FSUBrST0 },
};
/// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
/// instructions which need to be simplified and possibly transformed.
///
/// Result: ST(0) = fsub ST(0), ST(i)
/// ST(i) = fsub ST(0), ST(i)
/// ST(0) = fsubr ST(0), ST(i)
/// ST(i) = fsubr ST(0), ST(i)
///
void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
MachineInstr *MI = I;
unsigned NumOperands = MI->getNumOperands();
assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
unsigned Dest = getFPReg(MI->getOperand(0));
unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
bool KillsOp0 = false, KillsOp1 = false;
for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
E = LV->killed_end(MI); KI != E; ++KI) {
KillsOp0 |= (KI->second == X86::FP0+Op0);
KillsOp1 |= (KI->second == X86::FP0+Op1);
}
unsigned TOS = getStackEntry(0);
// One of our operands must be on the top of the stack. If neither is yet, we
// need to move one.
if (Op0 != TOS && Op1 != TOS) { // No operand at TOS?
// We can choose to move either operand to the top of the stack. If one of
// the operands is killed by this instruction, we want that one so that we
// can update right on top of the old version.
if (KillsOp0) {
moveToTop(Op0, I); // Move dead operand to TOS.
TOS = Op0;
} else if (KillsOp1) {
moveToTop(Op1, I);
TOS = Op1;
} else {
// All of the operands are live after this instruction executes, so we
// cannot update on top of any operand. Because of this, we must
// duplicate one of the stack elements to the top. It doesn't matter
// which one we pick.
//
duplicateToTop(Op0, Dest, I);
Op0 = TOS = Dest;
KillsOp0 = true;
}
} else if (!KillsOp0 && !KillsOp1) {
// If we DO have one of our operands at the top of the stack, but we don't
// have a dead operand, we must duplicate one of the operands to a new slot
// on the stack.
duplicateToTop(Op0, Dest, I);
Op0 = TOS = Dest;
KillsOp0 = true;
}
// Now we know that one of our operands is on the top of the stack, and at
// least one of our operands is killed by this instruction.
assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
"Stack conditions not set up right!");
// We decide which form to use based on what is on the top of the stack, and
// which operand is killed by this instruction.
const TableEntry *InstTable;
bool isForward = TOS == Op0;
bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
if (updateST0) {
if (isForward)
InstTable = ForwardST0Table;
else
InstTable = ReverseST0Table;
} else {
if (isForward)
InstTable = ForwardSTiTable;
else
InstTable = ReverseSTiTable;
}
int Opcode = Lookup(InstTable, ARRAY_SIZE(ForwardST0Table), MI->getOpcode());
assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
// NotTOS - The register which is not on the top of stack...
unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
// Replace the old instruction with a new instruction
MBB->remove(I++);
I = BuildMI(*MBB, I, Opcode, 1).addReg(getSTReg(NotTOS));
// If both operands are killed, pop one off of the stack in addition to
// overwriting the other one.
if (KillsOp0 && KillsOp1 && Op0 != Op1) {
assert(!updateST0 && "Should have updated other operand!");
popStackAfter(I); // Pop the top of stack
}
// Update stack information so that we know the destination register is now on
// the stack.
unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
assert(UpdatedSlot < StackTop && Dest < 7);
Stack[UpdatedSlot] = Dest;
RegMap[Dest] = UpdatedSlot;
delete MI; // Remove the old instruction
}
/// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
/// register arguments and no explicit destinations.
///
void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
MachineInstr *MI = I;
unsigned NumOperands = MI->getNumOperands();
assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
bool KillsOp0 = false, KillsOp1 = false;
for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
E = LV->killed_end(MI); KI != E; ++KI) {
KillsOp0 |= (KI->second == X86::FP0+Op0);
KillsOp1 |= (KI->second == X86::FP0+Op1);
}
// Make sure the first operand is on the top of stack, the other one can be
// anywhere.
moveToTop(Op0, I);
MI->getOperand(0).setReg(getSTReg(Op1));
MI->RemoveOperand(1);
// If any of the operands are killed by this instruction, free them.
if (KillsOp0) freeStackSlotAfter(I, Op0);
if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
}
/// handleCondMovFP - Handle two address conditional move instructions. These
/// instructions move a st(i) register to st(0) iff a condition is true. These
/// instructions require that the first operand is at the top of the stack, but
/// otherwise don't modify the stack at all.
void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
unsigned Op0 = getFPReg(MI->getOperand(0));
unsigned Op1 = getFPReg(MI->getOperand(1));
// The first operand *must* be on the top of the stack.
moveToTop(Op0, I);
// Change the second operand to the stack register that the operand is in.
MI->RemoveOperand(0);
MI->getOperand(0).setReg(getSTReg(Op1));
// If we kill the second operand, make sure to pop it from the stack.
if (Op0 != Op1)
for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
E = LV->killed_end(MI); KI != E; ++KI)
if (KI->second == X86::FP0+Op1) {
// Get this value off of the register stack.
freeStackSlotAfter(I, Op1);
break;
}
}
/// handleSpecialFP - Handle special instructions which behave unlike other
/// floating point instructions. This is primarily intended for use by pseudo
/// instructions.
///
void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
switch (MI->getOpcode()) {
default: assert(0 && "Unknown SpecialFP instruction!");
case X86::FpGETRESULT: // Appears immediately after a call returning FP type!
assert(StackTop == 0 && "Stack should be empty after a call!");
pushReg(getFPReg(MI->getOperand(0)));
break;
case X86::FpSETRESULT:
assert(StackTop == 1 && "Stack should have one element on it to return!");
--StackTop; // "Forget" we have something on the top of stack!
break;
case X86::FpMOV: {
unsigned SrcReg = getFPReg(MI->getOperand(1));
unsigned DestReg = getFPReg(MI->getOperand(0));
bool KillsSrc = false;
for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
E = LV->killed_end(MI); KI != E; ++KI)
KillsSrc |= KI->second == X86::FP0+SrcReg;
if (KillsSrc) {
// If the input operand is killed, we can just change the owner of the
// incoming stack slot into the result.
unsigned Slot = getSlot(SrcReg);
assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!");
Stack[Slot] = DestReg;
RegMap[DestReg] = Slot;
} else {
// For FMOV we just duplicate the specified value to a new stack slot.
// This could be made better, but would require substantial changes.
duplicateToTop(SrcReg, DestReg, I);
}
break;
}
}
I = MBB->erase(I); // Remove the pseudo instruction
--I;
}

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lib/Target/X86/InstSelectPattern.cpp
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//===-- InstSelectPattern.cpp - A pattern matching inst selector for X86 --===//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines a pattern matching instruction selector for X86.
//
// FIXME: we could allocate one big array of unsigneds to use as the backing
// store for all of the nodes costs arrays.
//
//===----------------------------------------------------------------------===//
#include "X86.h"
#include "llvm/Pass.h"
#include "llvm/Function.h"
#include "llvm/DerivedTypes.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "X86RegisterInfo.h"
#include <iostream>
// Include the generated instruction selector...
#include "X86GenInstrSelector.inc"
using namespace llvm;
namespace {
struct ISel : public FunctionPass, SelectionDAGTargetBuilder {
TargetMachine &TM;
ISel(TargetMachine &tm) : TM(tm) {}
int VarArgsFrameIndex; // FrameIndex for start of varargs area
bool runOnFunction(Function &Fn) {
MachineFunction &MF = MachineFunction::construct(&Fn, TM);
SelectionDAG DAG(MF, TM, *this);
std::cerr << "\n\n\n=== "
<< DAG.getMachineFunction().getFunction()->getName() << "\n";
DAG.dump();
X86ISel(DAG).generateCode();
std::cerr << "\n\n\n";
return true;
}
public: // Implementation of the SelectionDAGTargetBuilder class...
/// expandArguments - Add nodes to the DAG to indicate how to load arguments
/// off of the X86 stack.
void expandArguments(SelectionDAG &SD);
void expandCall(SelectionDAG &SD, CallInst &CI);
};
}
void ISel::expandArguments(SelectionDAG &SD) {
// Add DAG nodes to load the arguments... On entry to a function on the X86,
// the stack frame looks like this:
//
// [ESP] -- return address
// [ESP + 4] -- first argument (leftmost lexically)
// [ESP + 8] -- second argument, if first argument is four bytes in size
// ...
//
MachineFunction &F = SD.getMachineFunction();
MachineFrameInfo *MFI = F.getFrameInfo();
const Function &Fn = *F.getFunction();
unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
for (Function::const_aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
MVT::ValueType ObjectVT = SD.getValueType(I->getType());
unsigned ArgIncrement = 4;
unsigned ObjSize;
switch (ObjectVT) {
default: assert(0 && "Unhandled argument type!");
case MVT::i8: ObjSize = 1; break;
case MVT::i16: ObjSize = 2; break;
case MVT::i32: ObjSize = 4; break;
case MVT::i64: ObjSize = ArgIncrement = 8; break;
case MVT::f32: ObjSize = 4; break;
case MVT::f64: ObjSize = ArgIncrement = 8; break;
}
// Create the frame index object for this incoming parameter...
int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
// Create the SelectionDAG nodes corresponding to a load from this parameter
SelectionDAGNode *FIN = new SelectionDAGNode(ISD::FrameIndex, MVT::i32);
FIN->addValue(new ReducedValue_FrameIndex_i32(FI));
SelectionDAGNode *Arg
= new SelectionDAGNode(ISD::Load, ObjectVT, F.begin(), FIN);
// Add the SelectionDAGNodes to the SelectionDAG... note that there is no
// reason to add chain nodes here. We know that no loads ore stores will
// ever alias these loads, so we are free to perform the load at any time in
// the function
SD.addNode(FIN);
SD.addNodeForValue(Arg, I);
ArgOffset += ArgIncrement; // Move on to the next argument...
}
// If the function takes variable number of arguments, make a frame index for
// the start of the first vararg value... for expansion of llvm.va_start.
if (Fn.getFunctionType()->isVarArg())
VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
}
void ISel::expandCall(SelectionDAG &SD, CallInst &CI) {
assert(0 && "ISel::expandCall not implemented!");
}
/// createX86PatternInstructionSelector - This pass converts an LLVM function
/// into a machine code representation using pattern matching and a machine
/// description file.
///
FunctionPass *llvm::createX86PatternInstructionSelector(TargetMachine &TM) {
return new ISel(TM);
}

3907
lib/Target/X86/InstSelectSimple.cpp
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515
lib/Target/X86/PeepholeOptimizer.cpp
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//===-- PeepholeOptimizer.cpp - X86 Peephole Optimizer --------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains a peephole optimizer for the X86.
//
//===----------------------------------------------------------------------===//
#include "X86.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "Support/Statistic.h"
#include "Support/STLExtras.h"
using namespace llvm;
namespace {
Statistic<> NumPHOpts("x86-peephole",
"Number of peephole optimization performed");
Statistic<> NumPHMoves("x86-peephole", "Number of peephole moves folded");
struct PH : public MachineFunctionPass {
virtual bool runOnMachineFunction(MachineFunction &MF);
bool PeepholeOptimize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &I);
virtual const char *getPassName() const { return "X86 Peephole Optimizer"; }
};
}
FunctionPass *llvm::createX86PeepholeOptimizerPass() { return new PH(); }
bool PH::runOnMachineFunction(MachineFunction &MF) {
bool Changed = false;
for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI != E; ++BI)
for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); )
if (PeepholeOptimize(*BI, I)) {
Changed = true;
++NumPHOpts;
} else
++I;
return Changed;
}
bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &I) {
assert(I != MBB.end());
MachineBasicBlock::iterator NextI = next(I);
MachineInstr *MI = I;
MachineInstr *Next = (NextI != MBB.end()) ? &*NextI : (MachineInstr*)0;
unsigned Size = 0;
switch (MI->getOpcode()) {
case X86::MOV8rr:
case X86::MOV16rr:
case X86::MOV32rr: // Destroy X = X copies...
if (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
I = MBB.erase(I);
return true;
}
return false;
// A large number of X86 instructions have forms which take an 8-bit
// immediate despite the fact that the operands are 16 or 32 bits. Because
// this can save three bytes of code size (and icache space), we want to
// shrink them if possible.
case X86::IMUL16rri: case X86::IMUL32rri:
assert(MI->getNumOperands() == 3 && "These should all have 3 operands!");
if (MI->getOperand(2).isImmediate()) {
int Val = MI->getOperand(2).getImmedValue();
// If the value is the same when signed extended from 8 bits...
if (Val == (signed int)(signed char)Val) {
unsigned Opcode;
switch (MI->getOpcode()) {
default: assert(0 && "Unknown opcode value!");
case X86::IMUL16rri: Opcode = X86::IMUL16rri8; break;
case X86::IMUL32rri: Opcode = X86::IMUL32rri8; break;
}
unsigned R0 = MI->getOperand(0).getReg();
unsigned R1 = MI->getOperand(1).getReg();
I = MBB.insert(MBB.erase(I),
BuildMI(Opcode, 2, R0).addReg(R1).addZImm((char)Val));
return true;
}
}
return false;
#if 0
case X86::IMUL16rmi: case X86::IMUL32rmi:
assert(MI->getNumOperands() == 6 && "These should all have 6 operands!");
if (MI->getOperand(5).isImmediate()) {
int Val = MI->getOperand(5).getImmedValue();
// If the value is the same when signed extended from 8 bits...
if (Val == (signed int)(signed char)Val) {
unsigned Opcode;
switch (MI->getOpcode()) {
default: assert(0 && "Unknown opcode value!");
case X86::IMUL16rmi: Opcode = X86::IMUL16rmi8; break;
case X86::IMUL32rmi: Opcode = X86::IMUL32rmi8; break;
}
unsigned R0 = MI->getOperand(0).getReg();
unsigned R1 = MI->getOperand(1).getReg();
unsigned Scale = MI->getOperand(2).getImmedValue();
unsigned R2 = MI->getOperand(3).getReg();
unsigned Offset = MI->getOperand(4).getImmedValue();
I = MBB.insert(MBB.erase(I),
BuildMI(Opcode, 5, R0).addReg(R1).addZImm(Scale).
addReg(R2).addSImm(Offset).addZImm((char)Val));
return true;
}
}
return false;
#endif
case X86::ADD16ri: case X86::ADD32ri: case X86::ADC32ri:
case X86::SUB16ri: case X86::SUB32ri: case X86::SBB32ri:
case X86::AND16ri: case X86::AND32ri:
case X86::OR16ri: case X86::OR32ri:
case X86::XOR16ri: case X86::XOR32ri:
assert(MI->getNumOperands() == 2 && "These should all have 2 operands!");
if (MI->getOperand(1).isImmediate()) {
int Val = MI->getOperand(1).getImmedValue();
// If the value is the same when signed extended from 8 bits...
if (Val == (signed int)(signed char)Val) {
unsigned Opcode;
switch (MI->getOpcode()) {
default: assert(0 && "Unknown opcode value!");
case X86::ADD16ri: Opcode = X86::ADD16ri8; break;
case X86::ADD32ri: Opcode = X86::ADD32ri8; break;
case X86::ADC32ri: Opcode = X86::ADC32ri8; break;
case X86::SUB16ri: Opcode = X86::SUB16ri8; break;
case X86::SUB32ri: Opcode = X86::SUB32ri8; break;
case X86::SBB32ri: Opcode = X86::SBB32ri8; break;
case X86::AND16ri: Opcode = X86::AND16ri8; break;
case X86::AND32ri: Opcode = X86::AND32ri8; break;
case X86::OR16ri: Opcode = X86::OR16ri8; break;
case X86::OR32ri: Opcode = X86::OR32ri8; break;
case X86::XOR16ri: Opcode = X86::XOR16ri8; break;
case X86::XOR32ri: Opcode = X86::XOR32ri8; break;
}
unsigned R0 = MI->getOperand(0).getReg();
I = MBB.insert(MBB.erase(I),
BuildMI(Opcode, 1, R0, MachineOperand::UseAndDef)
.addZImm((char)Val));
return true;
}
}
return false;
case X86::ADD16mi: case X86::ADD32mi: case X86::ADC32mi:
case X86::SUB16mi: case X86::SUB32mi: case X86::SBB32mi:
case X86::AND16mi: case X86::AND32mi:
case X86::OR16mi: case X86::OR32mi:
case X86::XOR16mi: case X86::XOR32mi:
assert(MI->getNumOperands() == 5 && "These should all have 5 operands!");
if (MI->getOperand(4).isImmediate()) {
int Val = MI->getOperand(4).getImmedValue();
// If the value is the same when signed extended from 8 bits...
if (Val == (signed int)(signed char)Val) {
unsigned Opcode;
switch (MI->getOpcode()) {
default: assert(0 && "Unknown opcode value!");
case X86::ADD16mi: Opcode = X86::ADD16mi8; break;
case X86::ADD32mi: Opcode = X86::ADD32mi8; break;
case X86::ADC32mi: Opcode = X86::ADC32mi8; break;
case X86::SUB16mi: Opcode = X86::SUB16mi8; break;
case X86::SUB32mi: Opcode = X86::SUB32mi8; break;
case X86::SBB32mi: Opcode = X86::SBB32mi8; break;
case X86::AND16mi: Opcode = X86::AND16mi8; break;
case X86::AND32mi: Opcode = X86::AND32mi8; break;
case X86::OR16mi: Opcode = X86::OR16mi8; break;
case X86::OR32mi: Opcode = X86::OR32mi8; break;
case X86::XOR16mi: Opcode = X86::XOR16mi8; break;
case X86::XOR32mi: Opcode = X86::XOR32mi8; break;
}
unsigned R0 = MI->getOperand(0).getReg();
unsigned Scale = MI->getOperand(1).getImmedValue();
unsigned R1 = MI->getOperand(2).getReg();
unsigned Offset = MI->getOperand(3).getImmedValue();
I = MBB.insert(MBB.erase(I),
BuildMI(Opcode, 5).addReg(R0).addZImm(Scale).
addReg(R1).addSImm(Offset).addZImm((char)Val));
return true;
}
}
return false;
#if 0
case X86::MOV32ri: Size++;
case X86::MOV16ri: Size++;
case X86::MOV8ri:
// FIXME: We can only do this transformation if we know that flags are not
// used here, because XOR clobbers the flags!
if (MI->getOperand(1).isImmediate()) { // avoid mov EAX, <value>
int Val = MI->getOperand(1).getImmedValue();
if (Val == 0) { // mov EAX, 0 -> xor EAX, EAX
static const unsigned Opcode[] ={X86::XOR8rr,X86::XOR16rr,X86::XOR32rr};
unsigned Reg = MI->getOperand(0).getReg();
I = MBB.insert(MBB.erase(I),
BuildMI(Opcode[Size], 2, Reg).addReg(Reg).addReg(Reg));
return true;
} else if (Val == -1) { // mov EAX, -1 -> or EAX, -1
// TODO: 'or Reg, -1' has a smaller encoding than 'mov Reg, -1'
}
}
return false;
#endif
case X86::BSWAP32r: // Change bswap EAX, bswap EAX into nothing
if (Next->getOpcode() == X86::BSWAP32r &&
MI->getOperand(0).getReg() == Next->getOperand(0).getReg()) {
I = MBB.erase(MBB.erase(I));
return true;
}
return false;
default:
return false;
}
}
namespace {
class UseDefChains : public MachineFunctionPass {
std::vector<MachineInstr*> DefiningInst;
public:
// getDefinition - Return the machine instruction that defines the specified
// SSA virtual register.
MachineInstr *getDefinition(unsigned Reg) {
assert(MRegisterInfo::isVirtualRegister(Reg) &&
"use-def chains only exist for SSA registers!");
assert(Reg - MRegisterInfo::FirstVirtualRegister < DefiningInst.size() &&
"Unknown register number!");
assert(DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister] &&
"Unknown register number!");
return DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister];
}
// setDefinition - Update the use-def chains to indicate that MI defines
// register Reg.
void setDefinition(unsigned Reg, MachineInstr *MI) {
if (Reg-MRegisterInfo::FirstVirtualRegister >= DefiningInst.size())
DefiningInst.resize(Reg-MRegisterInfo::FirstVirtualRegister+1);
DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister] = MI;
}
// removeDefinition - Update the use-def chains to forget about Reg
// entirely.
void removeDefinition(unsigned Reg) {
assert(getDefinition(Reg)); // Check validity
DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister] = 0;
}
virtual bool runOnMachineFunction(MachineFunction &MF) {
for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI!=E; ++BI)
for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); ++I) {
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
MachineOperand &MO = I->getOperand(i);
if (MO.isRegister() && MO.isDef() && !MO.isUse() &&
MRegisterInfo::isVirtualRegister(MO.getReg()))
setDefinition(MO.getReg(), I);
}
}
return false;
}
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesAll();
MachineFunctionPass::getAnalysisUsage(AU);
}
virtual void releaseMemory() {
std::vector<MachineInstr*>().swap(DefiningInst);
}
};
RegisterAnalysis<UseDefChains> X("use-def-chains",
"use-def chain construction for machine code");
}
namespace {
Statistic<> NumSSAPHOpts("x86-ssa-peephole",
"Number of SSA peephole optimization performed");
/// SSAPH - This pass is an X86-specific, SSA-based, peephole optimizer. This
/// pass is really a bad idea: a better instruction selector should completely
/// supersume it. However, that will take some time to develop, and the
/// simple things this can do are important now.
class SSAPH : public MachineFunctionPass {
UseDefChains *UDC;
public:
virtual bool runOnMachineFunction(MachineFunction &MF);
bool PeepholeOptimize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &I);
virtual const char *getPassName() const {
return "X86 SSA-based Peephole Optimizer";
}
/// Propagate - Set MI[DestOpNo] = Src[SrcOpNo], optionally change the
/// opcode of the instruction, then return true.
bool Propagate(MachineInstr *MI, unsigned DestOpNo,
MachineInstr *Src, unsigned SrcOpNo, unsigned NewOpcode = 0){
MI->getOperand(DestOpNo) = Src->getOperand(SrcOpNo);
if (NewOpcode) MI->setOpcode(NewOpcode);
return true;
}
/// OptimizeAddress - If we can fold the addressing arithmetic for this
/// memory instruction into the instruction itself, do so and return true.
bool OptimizeAddress(MachineInstr *MI, unsigned OpNo);
/// getDefininingInst - If the specified operand is a read of an SSA
/// register, return the machine instruction defining it, otherwise, return
/// null.
MachineInstr *getDefiningInst(MachineOperand &MO) {
if (MO.isDef() || !MO.isRegister() ||
!MRegisterInfo::isVirtualRegister(MO.getReg())) return 0;
return UDC->getDefinition(MO.getReg());
}
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<UseDefChains>();
AU.addPreserved<UseDefChains>();
MachineFunctionPass::getAnalysisUsage(AU);
}
};
}
FunctionPass *llvm::createX86SSAPeepholeOptimizerPass() { return new SSAPH(); }
bool SSAPH::runOnMachineFunction(MachineFunction &MF) {
bool Changed = false;
bool LocalChanged;
UDC = &getAnalysis<UseDefChains>();
do {
LocalChanged = false;
for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI != E; ++BI)
for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); )
if (PeepholeOptimize(*BI, I)) {
LocalChanged = true;
++NumSSAPHOpts;
} else
++I;
Changed |= LocalChanged;
} while (LocalChanged);
return Changed;
}
static bool isValidScaleAmount(unsigned Scale) {
return Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8;
}
/// OptimizeAddress - If we can fold the addressing arithmetic for this
/// memory instruction into the instruction itself, do so and return true.
bool SSAPH::OptimizeAddress(MachineInstr *MI, unsigned OpNo) {
MachineOperand &BaseRegOp = MI->getOperand(OpNo+0);
MachineOperand &ScaleOp = MI->getOperand(OpNo+1);
MachineOperand &IndexRegOp = MI->getOperand(OpNo+2);
MachineOperand &DisplacementOp = MI->getOperand(OpNo+3);
unsigned BaseReg = BaseRegOp.hasAllocatedReg() ? BaseRegOp.getReg() : 0;
unsigned Scale = ScaleOp.getImmedValue();
unsigned IndexReg = IndexRegOp.hasAllocatedReg() ? IndexRegOp.getReg() : 0;
bool Changed = false;
// If the base register is unset, and the index register is set with a scale
// of 1, move it to be the base register.
if (BaseRegOp.hasAllocatedReg() && BaseReg == 0 &&
Scale == 1 && IndexReg != 0) {
BaseRegOp.setReg(IndexReg);
IndexRegOp.setReg(0);
return true;
}
// Attempt to fold instructions used by the base register into the instruction
if (MachineInstr *DefInst = getDefiningInst(BaseRegOp)) {
switch (DefInst->getOpcode()) {
case X86::MOV32ri:
// If there is no displacement set for this instruction set one now.
// FIXME: If we can fold two immediates together, we should do so!
if (DisplacementOp.isImmediate() && !DisplacementOp.getImmedValue()) {
if (DefInst->getOperand(1).isImmediate()) {
BaseRegOp.setReg(0);
return Propagate(MI, OpNo+3, DefInst, 1);
}
}
break;
case X86::ADD32rr:
// If the source is a register-register add, and we do not yet have an
// index register, fold the add into the memory address.
if (IndexReg == 0) {
BaseRegOp = DefInst->getOperand(1);
IndexRegOp = DefInst->getOperand(2);
ScaleOp.setImmedValue(1);
return true;
}
break;
case X86::SHL32ri:
// If this shift could be folded into the index portion of the address if
// it were the index register, move it to the index register operand now,
// so it will be folded in below.
if ((Scale == 1 || (IndexReg == 0 && IndexRegOp.hasAllocatedReg())) &&
DefInst->getOperand(2).getImmedValue() < 4) {
std::swap(BaseRegOp, IndexRegOp);
ScaleOp.setImmedValue(1); Scale = 1;
std::swap(IndexReg, BaseReg);
Changed = true;
break;
}
}
}
// Attempt to fold instructions used by the index into the instruction
if (MachineInstr *DefInst = getDefiningInst(IndexRegOp)) {
switch (DefInst->getOpcode()) {
case X86::SHL32ri: {
// Figure out what the resulting scale would be if we folded this shift.
unsigned ResScale = Scale * (1 << DefInst->getOperand(2).getImmedValue());
if (isValidScaleAmount(ResScale)) {
IndexRegOp = DefInst->getOperand(1);
ScaleOp.setImmedValue(ResScale);
return true;
}
break;
}
}
}
return Changed;
}
bool SSAPH::PeepholeOptimize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &I) {
MachineBasicBlock::iterator NextI = next(I);
MachineInstr *MI = I;
MachineInstr *Next = (NextI != MBB.end()) ? &*NextI : (MachineInstr*)0;
bool Changed = false;
const TargetInstrInfo &TII = *MBB.getParent()->getTarget().getInstrInfo();
// Scan the operands of this instruction. If any operands are
// register-register copies, replace the operand with the source.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
// Is this an SSA register use?
if (MachineInstr *DefInst = getDefiningInst(MI->getOperand(i))) {
// If the operand is a vreg-vreg copy, it is always safe to replace the
// source value with the input operand.
unsigned Source, Dest;
if (TII.isMoveInstr(*DefInst, Source, Dest)) {
// Don't propagate physical registers into any instructions.
if (DefInst->getOperand(1).isRegister() &&
MRegisterInfo::isVirtualRegister(Source)) {
MI->getOperand(i).setReg(Source);
Changed = true;
++NumPHMoves;
}
}
}
// Perform instruction specific optimizations.
switch (MI->getOpcode()) {
// Register to memory stores. Format: <base,scale,indexreg,immdisp>, srcreg
case X86::MOV32mr: case X86::MOV16mr: case X86::MOV8mr:
case X86::MOV32mi: case X86::MOV16mi: case X86::MOV8mi:
// Check to see if we can fold the source instruction into this one...
if (MachineInstr *SrcInst = getDefiningInst(MI->getOperand(4))) {
switch (SrcInst->getOpcode()) {
// Fold the immediate value into the store, if possible.
case X86::MOV8ri: return Propagate(MI, 4, SrcInst, 1, X86::MOV8mi);
case X86::MOV16ri: return Propagate(MI, 4, SrcInst, 1, X86::MOV16mi);
case X86::MOV32ri: return Propagate(MI, 4, SrcInst, 1, X86::MOV32mi);
default: break;
}
}
// If we can optimize the addressing expression, do so now.
if (OptimizeAddress(MI, 0))
return true;
break;
case X86::MOV32rm:
case X86::MOV16rm:
case X86::MOV8rm:
// If we can optimize the addressing expression, do so now.
if (OptimizeAddress(MI, 1))
return true;
break;
default: break;
}
return Changed;
}

1033
lib/Target/X86/Printer.cpp
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