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[ARM GlobalISel] Fix selecting G_BRCOND

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When lowering a G_BRCOND, we generate a TSTri of the condition against
1, which sets the flags, and then a Bcc which branches based on the
value of the flags.

Unfortunately, we were using the wrong condition code to check whether
we need to branch (EQ instead of NE), which caused all our branches to
do the opposite of what they were intended to do. This patch fixes the
issue by using the correct condition code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319313 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Diana Picus 2017-11-29 14:20:06 +00:00
parent abf3849506
commit c7436ce110
3 changed files with 3 additions and 3 deletions
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2
lib/Target/ARM/ARMInstructionSelector.cpp
View File

@ -855,7 +855,7 @@ bool ARMInstructionSelector::select(MachineInstr &I,
// Branch conditionally.
auto Branch = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(ARM::Bcc))
.add(I.getOperand(1))
.add(predOps(ARMCC::EQ, ARM::CPSR));
.add(predOps(ARMCC::NE, ARM::CPSR));
if (!constrainSelectedInstRegOperands(*Branch, TII, TRI, RBI))
return false;
I.eraseFromParent();

2
test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
View File

@ -1171,7 +1171,7 @@ body: |
G_BRCOND %1(s1), %bb.1
; CHECK: TSTri [[COND]], 1, 14, _, implicit-def %cpsr
; CHECK: Bcc %bb.1, 0, %cpsr
; CHECK: Bcc %bb.1, 1, %cpsr
G_BR %bb.2
; CHECK: B %bb.2

2
test/CodeGen/ARM/GlobalISel/arm-isel.ll
View File

@ -442,7 +442,7 @@ define arm_aapcscc void @test_brcond(i32 %n) {
; CHECK: cmp r0
; CHECK-NEXT: movgt [[RCMP:r[0-9]+]], #1
; CHECK: tst [[RCMP]], #1
; CHECK-NEXT: bne [[FALSE:.L[[:alnum:]_]+]]
; CHECK-NEXT: beq [[FALSE:.L[[:alnum:]_]+]]
; CHECK: bl brcond1
; CHECK: [[FALSE]]:
; CHECK: bl brcond2