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AVX-512: Added X86vzmovl patterns

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191733 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky 2013-10-01 08:38:02 +00:00
parent 18a8e10720
commit c8d0d00781
2 changed files with 21 additions and 0 deletions
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5
lib/Target/X86/X86InstrAVX512.td
View File

@ -1467,6 +1467,10 @@ let Predicates = [HasAVX512] in {
let AddedComplexity = 20 in {
def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
(VMOVDI2PDIZrm addr:$src)>;
def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
(VMOV64toPQIZrr GR64:$src)>;
def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
(VMOVDI2PDIZrr GR32:$src)>;
def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
(VMOVDI2PDIZrm addr:$src)>;
@ -1477,6 +1481,7 @@ let Predicates = [HasAVX512] in {
def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
(VMOVZPQILo2PQIZrr VR128X:$src)>;
}
// Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
(v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),

16
test/CodeGen/X86/avx512-mov.ll
View File

@ -100,3 +100,19 @@ define <2 x double> @test12(double* %x) {
%res = insertelement <2 x double>zeroinitializer, double %y, i32 0
ret <2 x double>%res
}
; CHECK-LABEL: @test13
; CHECK: vmovqz %rdi
; CHECK: ret
define <2 x i64> @test13(i64 %x) {
%res = insertelement <2 x i64>zeroinitializer, i64 %x, i32 0
ret <2 x i64>%res
}
; CHECK-LABEL: @test14
; CHECK: vmovdz %edi
; CHECK: ret
define <4 x i32> @test14(i32 %x) {
%res = insertelement <4 x i32>zeroinitializer, i32 %x, i32 0
ret <4 x i32>%res
}