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[mips] Rename HIRegs and LORegs.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188341 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2013-08-14 00:47:08 +00:00
parent 7cd85b7492
commit cbaf6d0cc3
10 changed files with 83 additions and 84 deletions
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36
lib/Target/Mips/Disassembler/MipsDisassembler.cpp
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@ -143,15 +143,15 @@ static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeHIRegsDSPRegisterClass(MCInst &Inst, static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeLORegsDSPRegisterClass(MCInst &Inst, static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeBranchTarget(MCInst &Inst, static DecodeStatus DecodeBranchTarget(MCInst &Inst,
unsigned Offset, unsigned Offset,
@ -489,26 +489,26 @@ static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeHIRegsDSPRegisterClass(MCInst &Inst, static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo >= 4) if (RegNo >= 4)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::HIRegsDSPRegClassID, RegNo); unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
Inst.addOperand(MCOperand::CreateReg(Reg)); Inst.addOperand(MCOperand::CreateReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeLORegsDSPRegisterClass(MCInst &Inst, static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo >= 4) if (RegNo >= 4)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::LORegsDSPRegClassID, RegNo); unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
Inst.addOperand(MCOperand::CreateReg(Reg)); Inst.addOperand(MCOperand::CreateReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }

4
lib/Target/Mips/MicroMipsInstrInfo.td
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@ -62,9 +62,9 @@ let DecoderNamespace = "MicroMips" in {
def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IIAlu, xor>, def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IIAlu, xor>,
ADD_FM_MM<0, 0x310>; ADD_FM_MM<0, 0x310>;
def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>; def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
def MULT_MM : MMRel, Mult<"mult", IIImul, GPR32Opnd, [HI, LO]>, def MULT_MM : MMRel, Mult<"mult", IIImul, GPR32Opnd, [HI0, LO0]>,
MULT_FM_MM<0x22c>; MULT_FM_MM<0x22c>;
def MULTu_MM : MMRel, Mult<"multu", IIImul, GPR32Opnd, [HI, LO]>, def MULTu_MM : MMRel, Mult<"multu", IIImul, GPR32Opnd, [HI0, LO0]>,
MULT_FM_MM<0x26c>; MULT_FM_MM<0x26c>;
/// Shift Instructions /// Shift Instructions

4
lib/Target/Mips/Mips16InstrInfo.cpp
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@ -77,11 +77,11 @@ void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
else if (Mips::GPR32RegClass.contains(DestReg) && else if (Mips::GPR32RegClass.contains(DestReg) &&
Mips::CPU16RegsRegClass.contains(SrcReg)) Mips::CPU16RegsRegClass.contains(SrcReg))
Opc = Mips::Move32R16; Opc = Mips::Move32R16;
else if ((SrcReg == Mips::HI) && else if ((SrcReg == Mips::HI0) &&
(Mips::CPU16RegsRegClass.contains(DestReg))) (Mips::CPU16RegsRegClass.contains(DestReg)))
Opc = Mips::Mfhi16, SrcReg = 0; Opc = Mips::Mfhi16, SrcReg = 0;
else if ((SrcReg == Mips::LO) && else if ((SrcReg == Mips::LO0) &&
(Mips::CPU16RegsRegClass.contains(DestReg))) (Mips::CPU16RegsRegClass.contains(DestReg)))
Opc = Mips::Mflo16, SrcReg = 0; Opc = Mips::Mflo16, SrcReg = 0;

16
lib/Target/Mips/Mips16InstrInfo.td
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@ -665,7 +665,7 @@ def CmpiRxImmX16: FEXT_RI16R_ins<0b01110, "cmpi", IIAlu> {
// To divide 32-bit signed integers. // To divide 32-bit signed integers.
// //
def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> { def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> {
let Defs = [HI, LO]; let Defs = [HI0, LO0];
} }
// //
@ -674,7 +674,7 @@ def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> {
// To divide 32-bit unsigned integers. // To divide 32-bit unsigned integers.
// //
def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> { def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> {
let Defs = [HI, LO]; let Defs = [HI0, LO0];
} }
// //
// Format: JAL target MIPS16e // Format: JAL target MIPS16e
@ -805,7 +805,7 @@ def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>;
// To copy the special purpose HI register to a GPR. // To copy the special purpose HI register to a GPR.
// //
def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> { def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> {
let Uses = [HI]; let Uses = [HI0];
let neverHasSideEffects = 1; let neverHasSideEffects = 1;
} }
@ -815,7 +815,7 @@ def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> {
// To copy the special purpose LO register to a GPR. // To copy the special purpose LO register to a GPR.
// //
def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> { def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> {
let Uses = [LO]; let Uses = [LO0];
let neverHasSideEffects = 1; let neverHasSideEffects = 1;
} }
@ -825,13 +825,13 @@ def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> {
def MultRxRy16: FMULT16_ins<"mult", IIAlu> { def MultRxRy16: FMULT16_ins<"mult", IIAlu> {
let isCommutable = 1; let isCommutable = 1;
let neverHasSideEffects = 1; let neverHasSideEffects = 1;
let Defs = [HI, LO]; let Defs = [HI0, LO0];
} }
def MultuRxRy16: FMULT16_ins<"multu", IIAlu> { def MultuRxRy16: FMULT16_ins<"multu", IIAlu> {
let isCommutable = 1; let isCommutable = 1;
let neverHasSideEffects = 1; let neverHasSideEffects = 1;
let Defs = [HI, LO]; let Defs = [HI0, LO0];
} }
// //
@ -842,7 +842,7 @@ def MultuRxRy16: FMULT16_ins<"multu", IIAlu> {
def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> { def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> {
let isCommutable = 1; let isCommutable = 1;
let neverHasSideEffects = 1; let neverHasSideEffects = 1;
let Defs = [HI, LO]; let Defs = [HI0, LO0];
} }
// //
@ -853,7 +853,7 @@ def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> {
def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> { def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> {
let isCommutable = 1; let isCommutable = 1;
let neverHasSideEffects = 1; let neverHasSideEffects = 1;
let Defs = [HI, LO]; let Defs = [HI0, LO0];
} }
// //

16
lib/Target/Mips/Mips64InstrInfo.td
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@ -187,26 +187,26 @@ def TAILCALL64_R : JumpFR<GPR64Opnd, MipsTailCall>, MTLO_FM<8>, IsTailCall;
} }
/// Multiply and Divide Instructions. /// Multiply and Divide Instructions.
def DMULT : Mult<"dmult", IIImult, GPR64Opnd, [HI64, LO64]>, def DMULT : Mult<"dmult", IIImult, GPR64Opnd, [HI0_64, LO0_64]>,
MULT_FM<0, 0x1c>; MULT_FM<0, 0x1c>;
def DMULTu : Mult<"dmultu", IIImult, GPR64Opnd, [HI64, LO64]>, def DMULTu : Mult<"dmultu", IIImult, GPR64Opnd, [HI0_64, LO0_64]>,
MULT_FM<0, 0x1d>; MULT_FM<0, 0x1d>;
def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult, def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
IIImult>; IIImult>;
def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu, def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
IIImult>; IIImult>;
def DSDIV : Div<"ddiv", IIIdiv, GPR64Opnd, [HI64, LO64]>, MULT_FM<0, 0x1e>; def DSDIV : Div<"ddiv", IIIdiv, GPR64Opnd, [HI0_64, LO0_64]>, MULT_FM<0, 0x1e>;
def DUDIV : Div<"ddivu", IIIdiv, GPR64Opnd, [HI64, LO64]>, MULT_FM<0, 0x1f>; def DUDIV : Div<"ddivu", IIIdiv, GPR64Opnd, [HI0_64, LO0_64]>, MULT_FM<0, 0x1f>;
def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem, def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem,
IIIdiv, 0, 1, 1>; IIIdiv, 0, 1, 1>;
def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU, def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU,
IIIdiv, 0, 1, 1>; IIIdiv, 0, 1, 1>;
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI64]>, MTLO_FM<0x11>; def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>;
def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO64]>, MTLO_FM<0x13>; def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>;
def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, [HI64]>, MFLO_FM<0x10>; def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, [HI0_64]>, MFLO_FM<0x10>;
def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, [LO64]>, MFLO_FM<0x12>; def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, [LO0_64]>, MFLO_FM<0x12>;
/// Sign Ext In Register Instructions. /// Sign Ext In Register Instructions.
def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd>, SEB_FM<0x10, 0x20>; def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd>, SEB_FM<0x10, 0x20>;

8
lib/Target/Mips/MipsDSPInstrInfo.td
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@ -737,10 +737,10 @@ class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR>,
Defs<[DSPOutFlag16_19]>; Defs<[DSPOutFlag16_19]>;
// Move from/to hi/lo. // Move from/to hi/lo.
class MFHI_DESC : MFHI_DESC_BASE<"mfhi", HIRegsDSP, NoItinerary>; class MFHI_DESC : MFHI_DESC_BASE<"mfhi", HI32DSP, NoItinerary>;
class MFLO_DESC : MFHI_DESC_BASE<"mflo", LORegsDSP, NoItinerary>; class MFLO_DESC : MFHI_DESC_BASE<"mflo", LO32DSP, NoItinerary>;
class MTHI_DESC : MTHI_DESC_BASE<"mthi", HIRegsDSP, NoItinerary>; class MTHI_DESC : MTHI_DESC_BASE<"mthi", HI32DSP, NoItinerary>;
class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LORegsDSP, NoItinerary>; class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LO32DSP, NoItinerary>;
// Dot product with accumulate/subtract // Dot product with accumulate/subtract
class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>; class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>;

10
lib/Target/Mips/MipsISelLowering.cpp
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@ -425,8 +425,8 @@ static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
return SDValue(); return SDValue();
EVT Ty = N->getValueType(0); EVT Ty = N->getValueType(0);
unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64; unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64; unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
MipsISD::DivRemU16; MipsISD::DivRemU16;
SDLoc DL(N); SDLoc DL(N);
@ -2924,7 +2924,7 @@ parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const {
return std::make_pair((unsigned)0, (const TargetRegisterClass*)0); return std::make_pair((unsigned)0, (const TargetRegisterClass*)0);
RC = TRI->getRegClass(Prefix == "hi" ? RC = TRI->getRegClass(Prefix == "hi" ?
Mips::HIRegsRegClassID : Mips::LORegsRegClassID); Mips::HI32RegClassID : Mips::LO32RegClassID);
return std::make_pair(*(RC->begin()), RC); return std::make_pair(*(RC->begin()), RC);
} }
@ -2992,8 +2992,8 @@ getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
case 'l': // register suitable for indirect jump case 'l': // register suitable for indirect jump
if (VT == MVT::i32) if (VT == MVT::i32)
return std::make_pair((unsigned)Mips::LO, &Mips::LORegsRegClass); return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
return std::make_pair((unsigned)Mips::LO64, &Mips::LORegs64RegClass); return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
case 'x': // register suitable for indirect jump case 'x': // register suitable for indirect jump
// Fixme: Not triggering the use of both hi and low // Fixme: Not triggering the use of both hi and low
// This will generate an error message // This will generate an error message

20
lib/Target/Mips/MipsInstrInfo.td
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@ -409,8 +409,8 @@ class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
class MArithR<string opstr, bit isComm = 0> : class MArithR<string opstr, bit isComm = 0> :
InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
!strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR> { !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR> {
let Defs = [HI, LO]; let Defs = [HI0, LO0];
let Uses = [HI, LO]; let Uses = [HI0, LO0];
let isCommutable = isComm; let isCommutable = isComm;
} }
@ -1042,23 +1042,23 @@ let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
} }
/// Multiply and Divide Instructions. /// Multiply and Divide Instructions.
def MULT : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI, LO]>, def MULT : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI0, LO0]>,
MULT_FM<0, 0x18>; MULT_FM<0, 0x18>;
def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI, LO]>, def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI0, LO0]>,
MULT_FM<0, 0x19>; MULT_FM<0, 0x19>;
def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, IIImult>; def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, IIImult>;
def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, IIImult>; def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, IIImult>;
def SDIV : Div<"div", IIIdiv, GPR32Opnd, [HI, LO]>, MULT_FM<0, 0x1a>; def SDIV : Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1a>;
def UDIV : Div<"divu", IIIdiv, GPR32Opnd, [HI, LO]>, MULT_FM<0, 0x1b>; def UDIV : Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1b>;
def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv, def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv,
0, 1, 1>; 0, 1, 1>;
def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv, def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv,
0, 1, 1>; 0, 1, 1>;
def MTHI : MoveToLOHI<"mthi", GPR32Opnd, [HI]>, MTLO_FM<0x11>; def MTHI : MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
def MTLO : MoveToLOHI<"mtlo", GPR32Opnd, [LO]>, MTLO_FM<0x13>; def MTLO : MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
def MFHI : MoveFromLOHI<"mfhi", GPR32Opnd, [HI]>, MFLO_FM<0x10>; def MFHI : MoveFromLOHI<"mfhi", GPR32Opnd, [HI0]>, MFLO_FM<0x10>;
def MFLO : MoveFromLOHI<"mflo", GPR32Opnd, [LO]>, MFLO_FM<0x12>; def MFLO : MoveFromLOHI<"mflo", GPR32Opnd, [LO0]>, MFLO_FM<0x12>;
/// Sign Ext In Register Instructions. /// Sign Ext In Register Instructions.
def SEB : SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM<0x10, 0x20>; def SEB : SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM<0x10, 0x20>;

29
lib/Target/Mips/MipsRegisterInfo.td
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@ -205,18 +205,18 @@ let Namespace = "Mips" in {
def W31 : AFPR128<31, "w31", [D31_64]>, DwarfRegNum<[63]>; def W31 : AFPR128<31, "w31", [D31_64]>, DwarfRegNum<[63]>;
// Hi/Lo registers // Hi/Lo registers
def HI : Register<"ac0">, DwarfRegNum<[64]>; def HI0 : Register<"ac0">, DwarfRegNum<[64]>;
def HI1 : Register<"ac1">, DwarfRegNum<[176]>; def HI1 : Register<"ac1">, DwarfRegNum<[176]>;
def HI2 : Register<"ac2">, DwarfRegNum<[178]>; def HI2 : Register<"ac2">, DwarfRegNum<[178]>;
def HI3 : Register<"ac3">, DwarfRegNum<[180]>; def HI3 : Register<"ac3">, DwarfRegNum<[180]>;
def LO : Register<"ac0">, DwarfRegNum<[65]>; def LO0 : Register<"ac0">, DwarfRegNum<[65]>;
def LO1 : Register<"ac1">, DwarfRegNum<[177]>; def LO1 : Register<"ac1">, DwarfRegNum<[177]>;
def LO2 : Register<"ac2">, DwarfRegNum<[179]>; def LO2 : Register<"ac2">, DwarfRegNum<[179]>;
def LO3 : Register<"ac3">, DwarfRegNum<[181]>; def LO3 : Register<"ac3">, DwarfRegNum<[181]>;
let SubRegIndices = [sub_32] in { let SubRegIndices = [sub_32] in {
def HI64 : RegisterWithSubRegs<"hi", [HI]>; def HI0_64 : RegisterWithSubRegs<"hi", [HI0]>;
def LO64 : RegisterWithSubRegs<"lo", [LO]>; def LO0_64 : RegisterWithSubRegs<"lo", [LO0]>;
} }
// FP control registers. // FP control registers.
@ -234,12 +234,11 @@ let Namespace = "Mips" in {
def HWR29 : MipsReg<29, "29">; def HWR29 : MipsReg<29, "29">;
// Accum registers // Accum registers
def AC0 : ACCReg<0, "ac0", [LO, HI]>; foreach I = 0-3 in
def AC1 : ACCReg<1, "ac1", [LO1, HI1]>; def AC#I : ACCReg<#I, "ac"#I,
def AC2 : ACCReg<2, "ac2", [LO2, HI2]>; [!cast<Register>("LO"#I), !cast<Register>("HI"#I)]>;
def AC3 : ACCReg<3, "ac3", [LO3, HI3]>;
def AC0_64 : ACCReg<0, "ac0", [LO64, HI64]>; def AC0_64 : ACCReg<0, "ac0", [LO0_64, HI0_64]>;
// DSP-ASE control register fields. // DSP-ASE control register fields.
def DSPPos : Register<"">; def DSPPos : Register<"">;
@ -348,12 +347,12 @@ def MSA128: RegisterClass<"Mips", [v16i8, v8i16, v4i32, v2i64], 128,
(sequence "W%u", 0, 31)>; (sequence "W%u", 0, 31)>;
// Hi/Lo Registers // Hi/Lo Registers
def LORegs : RegisterClass<"Mips", [i32], 32, (add LO)>; def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>;
def HIRegs : RegisterClass<"Mips", [i32], 32, (add HI)>; def HI32 : RegisterClass<"Mips", [i32], 32, (add HI0)>;
def LORegsDSP : RegisterClass<"Mips", [i32], 32, (add LO, LO1, LO2, LO3)>; def LO32DSP : RegisterClass<"Mips", [i32], 32, (sequence "LO%u", 0, 3)>;
def HIRegsDSP : RegisterClass<"Mips", [i32], 32, (add HI, HI1, HI2, HI3)>; def HI32DSP : RegisterClass<"Mips", [i32], 32, (sequence "HI%u", 0, 3)>;
def LORegs64 : RegisterClass<"Mips", [i64], 64, (add LO64)>; def LO64 : RegisterClass<"Mips", [i64], 64, (add LO0_64)>;
def HIRegs64 : RegisterClass<"Mips", [i64], 64, (add HI64)>; def HI64 : RegisterClass<"Mips", [i64], 64, (add HI0_64)>;
// Hardware registers // Hardware registers
def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable; def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable;

24
lib/Target/Mips/MipsSEInstrInfo.cpp
View File

@ -101,13 +101,13 @@ void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
Opc = Mips::CFC1; Opc = Mips::CFC1;
else if (Mips::FGR32RegClass.contains(SrcReg)) else if (Mips::FGR32RegClass.contains(SrcReg))
Opc = Mips::MFC1; Opc = Mips::MFC1;
else if (Mips::HIRegsRegClass.contains(SrcReg)) else if (Mips::HI32RegClass.contains(SrcReg))
Opc = Mips::MFHI, SrcReg = 0; Opc = Mips::MFHI, SrcReg = 0;
else if (Mips::LORegsRegClass.contains(SrcReg)) else if (Mips::LO32RegClass.contains(SrcReg))
Opc = Mips::MFLO, SrcReg = 0; Opc = Mips::MFLO, SrcReg = 0;
else if (Mips::HIRegsDSPRegClass.contains(SrcReg)) else if (Mips::HI32DSPRegClass.contains(SrcReg))
Opc = Mips::MFHI_DSP; Opc = Mips::MFHI_DSP;
else if (Mips::LORegsDSPRegClass.contains(SrcReg)) else if (Mips::LO32DSPRegClass.contains(SrcReg))
Opc = Mips::MFLO_DSP; Opc = Mips::MFLO_DSP;
else if (Mips::DSPCCRegClass.contains(SrcReg)) { else if (Mips::DSPCCRegClass.contains(SrcReg)) {
BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4) BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
@ -120,13 +120,13 @@ void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
Opc = Mips::CTC1; Opc = Mips::CTC1;
else if (Mips::FGR32RegClass.contains(DestReg)) else if (Mips::FGR32RegClass.contains(DestReg))
Opc = Mips::MTC1; Opc = Mips::MTC1;
else if (Mips::HIRegsRegClass.contains(DestReg)) else if (Mips::HI32RegClass.contains(DestReg))
Opc = Mips::MTHI, DestReg = 0; Opc = Mips::MTHI, DestReg = 0;
else if (Mips::LORegsRegClass.contains(DestReg)) else if (Mips::LO32RegClass.contains(DestReg))
Opc = Mips::MTLO, DestReg = 0; Opc = Mips::MTLO, DestReg = 0;
else if (Mips::HIRegsDSPRegClass.contains(DestReg)) else if (Mips::HI32DSPRegClass.contains(DestReg))
Opc = Mips::MTHI_DSP; Opc = Mips::MTHI_DSP;
else if (Mips::LORegsDSPRegClass.contains(DestReg)) else if (Mips::LO32DSPRegClass.contains(DestReg))
Opc = Mips::MTLO_DSP; Opc = Mips::MTLO_DSP;
else if (Mips::DSPCCRegClass.contains(DestReg)) { else if (Mips::DSPCCRegClass.contains(DestReg)) {
BuildMI(MBB, I, DL, get(Mips::WRDSP)) BuildMI(MBB, I, DL, get(Mips::WRDSP))
@ -144,17 +144,17 @@ void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg. else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
if (Mips::GPR64RegClass.contains(SrcReg)) if (Mips::GPR64RegClass.contains(SrcReg))
Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64; Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
else if (Mips::HIRegs64RegClass.contains(SrcReg)) else if (Mips::HI64RegClass.contains(SrcReg))
Opc = Mips::MFHI64, SrcReg = 0; Opc = Mips::MFHI64, SrcReg = 0;
else if (Mips::LORegs64RegClass.contains(SrcReg)) else if (Mips::LO64RegClass.contains(SrcReg))
Opc = Mips::MFLO64, SrcReg = 0; Opc = Mips::MFLO64, SrcReg = 0;
else if (Mips::FGR64RegClass.contains(SrcReg)) else if (Mips::FGR64RegClass.contains(SrcReg))
Opc = Mips::DMFC1; Opc = Mips::DMFC1;
} }
else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg. else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
if (Mips::HIRegs64RegClass.contains(DestReg)) if (Mips::HI64RegClass.contains(DestReg))
Opc = Mips::MTHI64, DestReg = 0; Opc = Mips::MTHI64, DestReg = 0;
else if (Mips::LORegs64RegClass.contains(DestReg)) else if (Mips::LO64RegClass.contains(DestReg))
Opc = Mips::MTLO64, DestReg = 0; Opc = Mips::MTLO64, DestReg = 0;
else if (Mips::FGR64RegClass.contains(DestReg)) else if (Mips::FGR64RegClass.contains(DestReg))
Opc = Mips::DMTC1; Opc = Mips::DMTC1;