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[MIRParser] Allow generic register specification on operand.

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This completes r292321 by adding support for generic registers, e.g.:

  %2:_(s32) = G_ADD %0, %1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292550 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ahmed Bougacha 2017-01-20 00:29:59 +00:00
parent c5cf6c8ad5
commit cbd2ff78c0
2 changed files with 20 additions and 13 deletions
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30
lib/CodeGen/MIRParser/MIParser.cpp
View File

@ -883,8 +883,8 @@ bool MIParser::parseRegister(unsigned &Reg, VRegInfo *&Info) {
}
bool MIParser::parseRegisterClassOrBank(VRegInfo &RegInfo) {
if (Token.isNot(MIToken::Identifier))
return error("expected a register class or register bank name");
if (Token.isNot(MIToken::Identifier) && Token.isNot(MIToken::underscore))
return error("expected '_', register class, or register bank name");
StringRef::iterator Loc = Token.location();
StringRef Name = Token.stringValue();
@ -914,26 +914,30 @@ bool MIParser::parseRegisterClassOrBank(VRegInfo &RegInfo) {
llvm_unreachable("Unexpected register kind");
}
// Should be a register bank.
auto RBNameI = PFS.Names2RegBanks.find(Name);
lex();
if (RBNameI == PFS.Names2RegBanks.end())
return error(Loc, "expected a register class or register bank name");
// Should be a register bank or a generic register.
const RegisterBank *RegBank = nullptr;
if (Name != "_") {
auto RBNameI = PFS.Names2RegBanks.find(Name);
if (RBNameI == PFS.Names2RegBanks.end())
return error(Loc, "expected '_', register class, or register bank name");
RegBank = RBNameI->getValue();
}
lex();
const RegisterBank &RegBank = *RBNameI->getValue();
switch (RegInfo.Kind) {
case VRegInfo::UNKNOWN:
case VRegInfo::GENERIC:
case VRegInfo::REGBANK:
RegInfo.Kind = VRegInfo::REGBANK;
if (RegInfo.Explicit && RegInfo.D.RegBank != &RegBank)
return error(Loc, "conflicting register banks");
RegInfo.D.RegBank = &RegBank;
RegInfo.Kind = RegBank ? VRegInfo::REGBANK : VRegInfo::GENERIC;
if (RegInfo.Explicit && RegInfo.D.RegBank != RegBank)
return error(Loc, "conflicting generic register banks");
RegInfo.D.RegBank = RegBank;
RegInfo.Explicit = true;
return false;
case VRegInfo::NORMAL:
return error(Loc, "register class specification on normal register");
return error(Loc, "register bank specification on normal register");
}
llvm_unreachable("Unexpected register kind");
}

3
test/CodeGen/MIR/X86/register-operand-class.mir
View File

@ -10,6 +10,7 @@
# CHECK: - { id: 1, class: gr64 }
# CHECK: - { id: 2, class: gr32 }
# CHECK: - { id: 3, class: gr16 }
# CHECK: - { id: 4, class: _ }
name: func
body: |
bb.0:
@ -21,4 +22,6 @@ body: |
%3 : gr16 = COPY %bx
%bx = COPY %3 : gr16
%4 : _(s32) = COPY %edx
...