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Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or

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ANDi, when the instruction does not have any immediate operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135520 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2011-07-19 20:34:00 +00:00
parent 2317fe1584
commit cc7ecc7290
2 changed files with 30 additions and 29 deletions
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27
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -870,9 +870,10 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
.addReg(Mips::ZERO).addImm(MaskImm);
BuildMI(BB, dl, TII->get(Mips::SLL), Mask).addReg(MaskUpper).addReg(ShiftAmt);
BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
.addReg(ShiftAmt).addReg(MaskUpper);
BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Incr).addReg(ShiftAmt);
BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr);
// atomic.load.binop
@ -911,7 +912,7 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
} else {// atomic.swap
// and newval, incr2, mask
BuildMI(BB, dl, TII->get(Mips::ANDi), NewVal).addReg(Incr2).addReg(Mask);
BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
}
BuildMI(BB, dl, TII->get(Mips::AND), MaskOldVal0)
@ -933,8 +934,8 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
.addReg(OldVal).addReg(Mask);
BuildMI(BB, dl, TII->get(Mips::SRL), SrlRes)
.addReg(MaskedOldVal1).addReg(ShiftAmt);
BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
.addReg(ShiftAmt).addReg(MaskedOldVal1);
BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
.addReg(SrlRes).addImm(ShiftImm);
BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
@ -1097,17 +1098,17 @@ MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
.addReg(Mips::ZERO).addImm(MaskImm);
BuildMI(BB, dl, TII->get(Mips::SLL), Mask)
.addReg(MaskUpper).addReg(ShiftAmt);
BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
.addReg(ShiftAmt).addReg(MaskUpper);
BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal)
.addReg(CmpVal).addImm(MaskImm);
BuildMI(BB, dl, TII->get(Mips::SLL), ShiftedCmpVal)
.addReg(MaskedCmpVal).addReg(ShiftAmt);
BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal)
.addReg(ShiftAmt).addReg(MaskedCmpVal);
BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal)
.addReg(NewVal).addImm(MaskImm);
BuildMI(BB, dl, TII->get(Mips::SLL), ShiftedNewVal)
.addReg(MaskedNewVal).addReg(ShiftAmt);
BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal)
.addReg(ShiftAmt).addReg(MaskedNewVal);
// loop1MBB:
// ll oldval,0(alginedaddr)
@ -1142,8 +1143,8 @@ MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
BB = sinkMBB;
int64_t ShiftImm = (Size == 1) ? 24 : 16;
BuildMI(BB, dl, TII->get(Mips::SRL), SrlRes)
.addReg(MaskedOldVal0).addReg(ShiftAmt);
BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
.addReg(ShiftAmt).addReg(MaskedOldVal0);
BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
.addReg(SrlRes).addImm(ShiftImm);
BuildMI(BB, dl, TII->get(Mips::SRA), Dest)

32
test/CodeGen/Mips/atomic.ll
View File

@ -94,9 +94,9 @@ entry:
; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
; CHECK: ori $[[R5:[0-9]+]], $zero, 255
; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]]
; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
; CHECK: sll $[[R9:[0-9]+]], $4, $[[R4]]
; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
; CHECK: $[[BB0:[A-Z_0-9]+]]:
; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
@ -108,7 +108,7 @@ entry:
; CHECK: beq $[[R14]], $zero, $[[BB0]]
; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]]
; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
; CHECK: sra $2, $[[R17]], 24
}
@ -125,9 +125,9 @@ entry:
; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
; CHECK: ori $[[R5:[0-9]+]], $zero, 255
; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]]
; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
; CHECK: sll $[[R9:[0-9]+]], $4, $[[R4]]
; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
; CHECK: $[[BB0:[A-Z_0-9]+]]:
; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
@ -139,7 +139,7 @@ entry:
; CHECK: beq $[[R14]], $zero, $[[BB0]]
; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]]
; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
; CHECK: sra $2, $[[R17]], 24
}
@ -156,9 +156,9 @@ entry:
; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
; CHECK: ori $[[R5:[0-9]+]], $zero, 255
; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]]
; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
; CHECK: sll $[[R9:[0-9]+]], $4, $[[R4]]
; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
; CHECK: $[[BB0:[A-Z_0-9]+]]:
; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
@ -171,7 +171,7 @@ entry:
; CHECK: beq $[[R14]], $zero, $[[BB0]]
; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]]
; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
; CHECK: sra $2, $[[R17]], 24
}
@ -188,9 +188,9 @@ entry:
; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
; CHECK: ori $[[R5:[0-9]+]], $zero, 255
; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]]
; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
; CHECK: sll $[[R9:[0-9]+]], $4, $[[R4]]
; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
; CHECK: $[[BB0:[A-Z_0-9]+]]:
; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
@ -200,7 +200,7 @@ entry:
; CHECK: beq $[[R14]], $zero, $[[BB0]]
; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]]
; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
; CHECK: sra $2, $[[R17]], 24
}
@ -217,12 +217,12 @@ entry:
; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
; CHECK: ori $[[R5:[0-9]+]], $zero, 255
; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]]
; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
; CHECK: andi $[[R8:[0-9]+]], $4, 255
; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]]
; CHECK: sllv $[[R9:[0-9]+]], $[[R8]], $[[R4]]
; CHECK: andi $[[R10:[0-9]+]], $5, 255
; CHECK: sll $[[R11:[0-9]+]], $[[R10]], $[[R4]]
; CHECK: sllv $[[R11:[0-9]+]], $[[R10]], $[[R4]]
; CHECK: $[[BB0:[A-Z_0-9]+]]:
; CHECK: ll $[[R12:[0-9]+]], 0($[[R2]])
@ -235,7 +235,7 @@ entry:
; CHECK: beq $[[R15]], $zero, $[[BB0]]
; CHECK: $[[BB1]]:
; CHECK: srl $[[R16:[0-9]+]], $[[R13]], $[[R4]]
; CHECK: srlv $[[R16:[0-9]+]], $[[R13]], $[[R4]]
; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
; CHECK: sra $2, $[[R17]], 24
}