From ccfea35efb0817267a9b997933207863917a8a85 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Mon, 22 Feb 2010 00:28:59 +0000 Subject: [PATCH] fix an incorrect VT: eflags is always i32. The bug was causing us to create an X86ISD::Cmp node with result type i64 on the CodeGen/X86/shift-i256.ll testcase and the new isel was assert on it downstream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96768 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelLowering.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 750087a2815..3831066719b 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -5245,7 +5245,7 @@ SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) { SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, DAG.getConstant(VTBits, MVT::i8)); - SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT, + SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, AndNode, DAG.getConstant(0, MVT::i8)); SDValue Hi, Lo;