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[mips] Instruction selection patterns for DSP-ASE vector select and compare
instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180820 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
86a87d9ba1
commit
cd6c57917d
@ -79,6 +79,8 @@ def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>;
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def MipsSHLL_DSP : MipsDSPBase<"SHLL_DSP", SDT_MipsSHIFT_DSP>;
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def MipsSHRA_DSP : MipsDSPBase<"SHRA_DSP", SDT_MipsSHIFT_DSP>;
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def MipsSHRL_DSP : MipsDSPBase<"SHRL_DSP", SDT_MipsSHIFT_DSP>;
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def MipsSETCC_DSP : MipsDSPBase<"SETCC_DSP", SDTSetCC>;
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def MipsSELECT_CC_DSP : MipsDSPBase<"SELECT_CC_DSP", SDTSelectCC>;
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// Flags.
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class UseAC {
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@ -1237,6 +1239,26 @@ let isPseudo = 1 in {
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def COPY_AC_DSP : PseudoSE<(outs ACRegsDSP:$dst), (ins ACRegsDSP:$src), []>;
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// Pseudo CMP and PICK instructions.
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class PseudoCMP<Instruction RealInst> :
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PseudoDSP<(outs DSPCC:$cmp), (ins DSPRegs:$rs, DSPRegs:$rt), []>,
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PseudoInstExpansion<(RealInst DSPRegs:$rs, DSPRegs:$rt)>, NeverHasSideEffects;
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class PseudoPICK<Instruction RealInst> :
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PseudoDSP<(outs DSPRegs:$rd), (ins DSPCC:$cmp, DSPRegs:$rs, DSPRegs:$rt), []>,
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PseudoInstExpansion<(RealInst DSPRegs:$rd, DSPRegs:$rs, DSPRegs:$rt)>,
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NeverHasSideEffects;
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def PseudoCMP_EQ_PH : PseudoCMP<CMP_EQ_PH>;
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def PseudoCMP_LT_PH : PseudoCMP<CMP_LT_PH>;
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def PseudoCMP_LE_PH : PseudoCMP<CMP_LE_PH>;
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def PseudoCMPU_EQ_QB : PseudoCMP<CMPU_EQ_QB>;
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def PseudoCMPU_LT_QB : PseudoCMP<CMPU_LT_QB>;
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def PseudoCMPU_LE_QB : PseudoCMP<CMPU_LE_QB>;
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def PseudoPICK_PH : PseudoPICK<PICK_PH>;
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def PseudoPICK_QB : PseudoPICK<PICK_QB>;
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// Patterns.
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class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
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Pat<pattern, result>, Requires<[pred]>;
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@ -1298,6 +1320,57 @@ def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>;
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def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>;
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def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>;
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// SETCC/SELECT_CC patterns.
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class DSPSetCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
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CondCode CC> :
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DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
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(ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
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(ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPRegs)),
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(ValTy ZERO)))>;
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class DSPSetCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
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CondCode CC> :
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DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
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(ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
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(ValTy ZERO),
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(ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPRegs))))>;
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class DSPSelectCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
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CondCode CC> :
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DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
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(ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $c, $d))>;
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class DSPSelectCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
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CondCode CC> :
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DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
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(ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $d, $c))>;
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def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
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def : DSPSetCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
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def : DSPSetCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
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def : DSPSetCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
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def : DSPSetCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
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def : DSPSetCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
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def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
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def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
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def : DSPSetCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
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def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
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def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
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def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
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def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
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def : DSPSelectCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
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def : DSPSelectCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
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def : DSPSelectCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
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def : DSPSelectCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
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def : DSPSelectCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
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def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
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def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
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def : DSPSelectCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
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def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
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def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
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def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
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// Extr patterns.
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class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
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DSPPat<(i32 (OpNode CPURegs:$rs, ACRegsDSP:$ac)),
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@ -200,6 +200,8 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
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case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
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case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
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case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
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case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
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default: return NULL;
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}
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}
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@ -213,7 +215,7 @@ MipsTargetLowering(MipsTargetMachine &TM)
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// Mips does not have i1 type, so use i32 for
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// setcc operations results (slt, sgt, ...).
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setBooleanContents(ZeroOrOneBooleanContent);
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setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
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setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
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// Load extented operations for i1 types must be promoted
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setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
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@ -148,6 +148,10 @@ namespace llvm {
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SHRA_DSP,
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SHRL_DSP,
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// DSP setcc and select_cc nodes.
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SETCC_DSP,
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SELECT_CC_DSP,
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// Load/Store Left/Right nodes.
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LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
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LWR,
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@ -265,6 +265,7 @@ let Namespace = "Mips" in {
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def AC0_64 : ACC<0, "ac0", [LO64, HI64]>;
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def DSPCtrl : Register<"dspctrl">;
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def DSPCCond : Register<"">;
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}
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//===----------------------------------------------------------------------===//
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@ -362,6 +363,9 @@ def ACRegsDSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> {
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let Size = 64;
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}
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def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>;
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// Register Operands.
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def CPURegsAsmOperand : AsmOperandClass {
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let Name = "CPURegsAsm";
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let ParserMethod = "parseCPURegs";
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@ -56,6 +56,8 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
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setTargetDAGCombine(ISD::SHL);
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setTargetDAGCombine(ISD::SRA);
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setTargetDAGCombine(ISD::SRL);
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setTargetDAGCombine(ISD::SETCC);
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setTargetDAGCombine(ISD::VSELECT);
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}
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if (Subtarget->hasDSPR2())
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@ -373,9 +375,57 @@ static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
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return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
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}
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static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
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bool IsV216 = (Ty == MVT::v2i16);
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switch (CC) {
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case ISD::SETEQ:
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case ISD::SETNE: return true;
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case ISD::SETLT:
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case ISD::SETLE:
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case ISD::SETGT:
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case ISD::SETGE: return IsV216;
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case ISD::SETULT:
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case ISD::SETULE:
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case ISD::SETUGT:
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case ISD::SETUGE: return !IsV216;
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default: return false;
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}
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}
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static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
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EVT Ty = N->getValueType(0);
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if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
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return SDValue();
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if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
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return SDValue();
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return DAG.getNode(MipsISD::SETCC_DSP, N->getDebugLoc(), Ty, N->getOperand(0),
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N->getOperand(1), N->getOperand(2));
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}
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static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
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EVT Ty = N->getValueType(0);
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if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
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return SDValue();
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SDValue SetCC = N->getOperand(0);
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if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
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return SDValue();
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return DAG.getNode(MipsISD::SELECT_CC_DSP, N->getDebugLoc(), Ty,
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SetCC.getOperand(0), SetCC.getOperand(1), N->getOperand(1),
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N->getOperand(2), SetCC.getOperand(2));
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}
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SDValue
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MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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SDValue Val;
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switch (N->getOpcode()) {
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case ISD::ADDE:
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@ -388,9 +438,18 @@ MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
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return performSRACombine(N, DAG, DCI, Subtarget);
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case ISD::SRL:
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return performSRLCombine(N, DAG, DCI, Subtarget);
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default:
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return MipsTargetLowering::PerformDAGCombine(N, DCI);
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case ISD::VSELECT:
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return performVSELECTCombine(N, DAG);
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case ISD::SETCC: {
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Val = performSETCCCombine(N, DAG);
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break;
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}
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}
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if (Val.getNode())
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return Val;
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return MipsTargetLowering::PerformDAGCombine(N, DCI);
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}
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MachineBasicBlock *
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641
test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll
Normal file
641
test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll
Normal file
@ -0,0 +1,641 @@
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; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s
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; CHECK: select_v2q15_eq_:
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; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
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; CHECK: pick.ph ${{[0-9]+}}, $6, $7
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define { i32 } @select_v2q15_eq_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) {
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entry:
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%1 = bitcast i32 %a1.coerce to <2 x i16>
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%2 = bitcast i32 %a2.coerce to <2 x i16>
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%3 = bitcast i32 %a3.coerce to <2 x i16>
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%cmp = icmp eq <2 x i16> %0, %1
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%or = select <2 x i1> %cmp, <2 x i16> %2, <2 x i16> %3
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%4 = bitcast <2 x i16> %or to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0
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ret { i32 } %.fca.0.insert
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}
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; CHECK: select_v2q15_lt_:
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; CHECK: cmp.lt.ph $4, $5
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; CHECK: pick.ph ${{[0-9]+}}, $6, $7
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define { i32 } @select_v2q15_lt_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) {
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entry:
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%1 = bitcast i32 %a1.coerce to <2 x i16>
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%2 = bitcast i32 %a2.coerce to <2 x i16>
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%3 = bitcast i32 %a3.coerce to <2 x i16>
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%cmp = icmp slt <2 x i16> %0, %1
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%or = select <2 x i1> %cmp, <2 x i16> %2, <2 x i16> %3
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%4 = bitcast <2 x i16> %or to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0
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ret { i32 } %.fca.0.insert
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}
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; CHECK: select_v2q15_le_:
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; CHECK: cmp.le.ph $4, $5
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; CHECK: pick.ph ${{[0-9]+}}, $6, $7
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define { i32 } @select_v2q15_le_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) {
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entry:
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%1 = bitcast i32 %a1.coerce to <2 x i16>
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%2 = bitcast i32 %a2.coerce to <2 x i16>
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%3 = bitcast i32 %a3.coerce to <2 x i16>
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%cmp = icmp sle <2 x i16> %0, %1
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%or = select <2 x i1> %cmp, <2 x i16> %2, <2 x i16> %3
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%4 = bitcast <2 x i16> %or to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0
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ret { i32 } %.fca.0.insert
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}
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; CHECK: select_v2q15_ne_:
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; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
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; CHECK: pick.ph ${{[0-9]+}}, $7, $6
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define { i32 } @select_v2q15_ne_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) {
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entry:
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%1 = bitcast i32 %a1.coerce to <2 x i16>
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%2 = bitcast i32 %a2.coerce to <2 x i16>
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%3 = bitcast i32 %a3.coerce to <2 x i16>
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%cmp = icmp ne <2 x i16> %0, %1
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%or = select <2 x i1> %cmp, <2 x i16> %2, <2 x i16> %3
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%4 = bitcast <2 x i16> %or to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0
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ret { i32 } %.fca.0.insert
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}
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; CHECK: select_v2q15_gt_:
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; CHECK: cmp.le.ph $4, $5
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; CHECK: pick.ph ${{[0-9]+}}, $7, $6
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define { i32 } @select_v2q15_gt_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) {
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entry:
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%1 = bitcast i32 %a1.coerce to <2 x i16>
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%2 = bitcast i32 %a2.coerce to <2 x i16>
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%3 = bitcast i32 %a3.coerce to <2 x i16>
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%cmp = icmp sgt <2 x i16> %0, %1
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%or = select <2 x i1> %cmp, <2 x i16> %2, <2 x i16> %3
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%4 = bitcast <2 x i16> %or to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0
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ret { i32 } %.fca.0.insert
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}
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; CHECK: select_v2q15_ge_:
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; CHECK: cmp.lt.ph $4, $5
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; CHECK: pick.ph ${{[0-9]+}}, $7, $6
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define { i32 } @select_v2q15_ge_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) {
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entry:
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%1 = bitcast i32 %a1.coerce to <2 x i16>
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%2 = bitcast i32 %a2.coerce to <2 x i16>
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%3 = bitcast i32 %a3.coerce to <2 x i16>
|
||||
%cmp = icmp sge <2 x i16> %0, %1
|
||||
%or = select <2 x i1> %cmp, <2 x i16> %2, <2 x i16> %3
|
||||
%4 = bitcast <2 x i16> %or to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: select_v4ui8_eq_:
|
||||
; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; CHECK: pick.qb ${{[0-9]+}}, $6, $7
|
||||
|
||||
define { i32 } @select_v4ui8_eq_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = bitcast i32 %a1.coerce to <4 x i8>
|
||||
%2 = bitcast i32 %a2.coerce to <4 x i8>
|
||||
%3 = bitcast i32 %a3.coerce to <4 x i8>
|
||||
%cmp = icmp eq <4 x i8> %0, %1
|
||||
%or = select <4 x i1> %cmp, <4 x i8> %2, <4 x i8> %3
|
||||
%4 = bitcast <4 x i8> %or to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: select_v4ui8_lt_:
|
||||
; CHECK: cmpu.lt.qb $4, $5
|
||||
; CHECK: pick.qb ${{[0-9]+}}, $6, $7
|
||||
|
||||
define { i32 } @select_v4ui8_lt_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = bitcast i32 %a1.coerce to <4 x i8>
|
||||
%2 = bitcast i32 %a2.coerce to <4 x i8>
|
||||
%3 = bitcast i32 %a3.coerce to <4 x i8>
|
||||
%cmp = icmp ult <4 x i8> %0, %1
|
||||
%or = select <4 x i1> %cmp, <4 x i8> %2, <4 x i8> %3
|
||||
%4 = bitcast <4 x i8> %or to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: select_v4ui8_le_:
|
||||
; CHECK: cmpu.le.qb $4, $5
|
||||
; CHECK: pick.qb ${{[0-9]+}}, $6, $7
|
||||
|
||||
define { i32 } @select_v4ui8_le_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = bitcast i32 %a1.coerce to <4 x i8>
|
||||
%2 = bitcast i32 %a2.coerce to <4 x i8>
|
||||
%3 = bitcast i32 %a3.coerce to <4 x i8>
|
||||
%cmp = icmp ule <4 x i8> %0, %1
|
||||
%or = select <4 x i1> %cmp, <4 x i8> %2, <4 x i8> %3
|
||||
%4 = bitcast <4 x i8> %or to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: select_v4ui8_ne_:
|
||||
; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; CHECK: pick.qb ${{[0-9]+}}, $7, $6
|
||||
|
||||
define { i32 } @select_v4ui8_ne_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = bitcast i32 %a1.coerce to <4 x i8>
|
||||
%2 = bitcast i32 %a2.coerce to <4 x i8>
|
||||
%3 = bitcast i32 %a3.coerce to <4 x i8>
|
||||
%cmp = icmp ne <4 x i8> %0, %1
|
||||
%or = select <4 x i1> %cmp, <4 x i8> %2, <4 x i8> %3
|
||||
%4 = bitcast <4 x i8> %or to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: select_v4ui8_gt_:
|
||||
; CHECK: cmpu.le.qb $4, $5
|
||||
; CHECK: pick.qb ${{[0-9]+}}, $7, $6
|
||||
|
||||
define { i32 } @select_v4ui8_gt_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = bitcast i32 %a1.coerce to <4 x i8>
|
||||
%2 = bitcast i32 %a2.coerce to <4 x i8>
|
||||
%3 = bitcast i32 %a3.coerce to <4 x i8>
|
||||
%cmp = icmp ugt <4 x i8> %0, %1
|
||||
%or = select <4 x i1> %cmp, <4 x i8> %2, <4 x i8> %3
|
||||
%4 = bitcast <4 x i8> %or to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: select_v4ui8_ge_:
|
||||
; CHECK: cmpu.lt.qb $4, $5
|
||||
; CHECK: pick.qb ${{[0-9]+}}, $7, $6
|
||||
|
||||
define { i32 } @select_v4ui8_ge_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = bitcast i32 %a1.coerce to <4 x i8>
|
||||
%2 = bitcast i32 %a2.coerce to <4 x i8>
|
||||
%3 = bitcast i32 %a3.coerce to <4 x i8>
|
||||
%cmp = icmp uge <4 x i8> %0, %1
|
||||
%or = select <4 x i1> %cmp, <4 x i8> %2, <4 x i8> %3
|
||||
%4 = bitcast <4 x i8> %or to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: select_v2ui16_lt_:
|
||||
; CHECK-NOT: cmp
|
||||
; CHECK-NOT: pick
|
||||
|
||||
define { i32 } @select_v2ui16_lt_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%2 = bitcast i32 %a2.coerce to <2 x i16>
|
||||
%3 = bitcast i32 %a3.coerce to <2 x i16>
|
||||
%cmp = icmp ult <2 x i16> %0, %1
|
||||
%or = select <2 x i1> %cmp, <2 x i16> %2, <2 x i16> %3
|
||||
%4 = bitcast <2 x i16> %or to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: select_v2ui16_le_:
|
||||
; CHECK-NOT: cmp
|
||||
; CHECK-NOT: pick
|
||||
|
||||
define { i32 } @select_v2ui16_le_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%2 = bitcast i32 %a2.coerce to <2 x i16>
|
||||
%3 = bitcast i32 %a3.coerce to <2 x i16>
|
||||
%cmp = icmp ule <2 x i16> %0, %1
|
||||
%or = select <2 x i1> %cmp, <2 x i16> %2, <2 x i16> %3
|
||||
%4 = bitcast <2 x i16> %or to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: select_v2ui16_gt_:
|
||||
; CHECK-NOT: cmp
|
||||
; CHECK-NOT: pick
|
||||
|
||||
define { i32 } @select_v2ui16_gt_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%2 = bitcast i32 %a2.coerce to <2 x i16>
|
||||
%3 = bitcast i32 %a3.coerce to <2 x i16>
|
||||
%cmp = icmp ugt <2 x i16> %0, %1
|
||||
%or = select <2 x i1> %cmp, <2 x i16> %2, <2 x i16> %3
|
||||
%4 = bitcast <2 x i16> %or to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: select_v2ui16_ge_:
|
||||
; CHECK-NOT: cmp
|
||||
; CHECK-NOT: pick
|
||||
|
||||
define { i32 } @select_v2ui16_ge_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%2 = bitcast i32 %a2.coerce to <2 x i16>
|
||||
%3 = bitcast i32 %a3.coerce to <2 x i16>
|
||||
%cmp = icmp uge <2 x i16> %0, %1
|
||||
%or = select <2 x i1> %cmp, <2 x i16> %2, <2 x i16> %3
|
||||
%4 = bitcast <2 x i16> %or to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: select_v4i8_lt_:
|
||||
; CHECK-NOT: cmp
|
||||
; CHECK-NOT: pick
|
||||
|
||||
define { i32 } @select_v4i8_lt_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = bitcast i32 %a1.coerce to <4 x i8>
|
||||
%2 = bitcast i32 %a2.coerce to <4 x i8>
|
||||
%3 = bitcast i32 %a3.coerce to <4 x i8>
|
||||
%cmp = icmp slt <4 x i8> %0, %1
|
||||
%or = select <4 x i1> %cmp, <4 x i8> %2, <4 x i8> %3
|
||||
%4 = bitcast <4 x i8> %or to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: select_v4i8_le_:
|
||||
; CHECK-NOT: cmp
|
||||
; CHECK-NOT: pick
|
||||
|
||||
define { i32 } @select_v4i8_le_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = bitcast i32 %a1.coerce to <4 x i8>
|
||||
%2 = bitcast i32 %a2.coerce to <4 x i8>
|
||||
%3 = bitcast i32 %a3.coerce to <4 x i8>
|
||||
%cmp = icmp sle <4 x i8> %0, %1
|
||||
%or = select <4 x i1> %cmp, <4 x i8> %2, <4 x i8> %3
|
||||
%4 = bitcast <4 x i8> %or to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: select_v4i8_gt_:
|
||||
; CHECK-NOT: cmp
|
||||
; CHECK-NOT: pick
|
||||
|
||||
define { i32 } @select_v4i8_gt_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = bitcast i32 %a1.coerce to <4 x i8>
|
||||
%2 = bitcast i32 %a2.coerce to <4 x i8>
|
||||
%3 = bitcast i32 %a3.coerce to <4 x i8>
|
||||
%cmp = icmp sgt <4 x i8> %0, %1
|
||||
%or = select <4 x i1> %cmp, <4 x i8> %2, <4 x i8> %3
|
||||
%4 = bitcast <4 x i8> %or to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: select_v4i8_ge_:
|
||||
; CHECK-NOT: cmp
|
||||
; CHECK-NOT: pick
|
||||
|
||||
define { i32 } @select_v4i8_ge_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = bitcast i32 %a1.coerce to <4 x i8>
|
||||
%2 = bitcast i32 %a2.coerce to <4 x i8>
|
||||
%3 = bitcast i32 %a3.coerce to <4 x i8>
|
||||
%cmp = icmp sge <4 x i8> %0, %1
|
||||
%or = select <4 x i1> %cmp, <4 x i8> %2, <4 x i8> %3
|
||||
%4 = bitcast <4 x i8> %or to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: compare_v2q15_eq_:
|
||||
; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
|
||||
|
||||
define { i32 } @compare_v2q15_eq_(i32 %a0.coerce, i32 %a1.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%cmp = icmp eq <2 x i16> %0, %1
|
||||
%sext = sext <2 x i1> %cmp to <2 x i16>
|
||||
%2 = bitcast <2 x i16> %sext to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: compare_v2q15_lt_:
|
||||
; CHECK: cmp.lt.ph $4, $5
|
||||
; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
|
||||
|
||||
define { i32 } @compare_v2q15_lt_(i32 %a0.coerce, i32 %a1.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%cmp = icmp slt <2 x i16> %0, %1
|
||||
%sext = sext <2 x i1> %cmp to <2 x i16>
|
||||
%2 = bitcast <2 x i16> %sext to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: compare_v2q15_le_:
|
||||
; CHECK: cmp.le.ph $4, $5
|
||||
; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
|
||||
|
||||
define { i32 } @compare_v2q15_le_(i32 %a0.coerce, i32 %a1.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%cmp = icmp sle <2 x i16> %0, %1
|
||||
%sext = sext <2 x i1> %cmp to <2 x i16>
|
||||
%2 = bitcast <2 x i16> %sext to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: compare_v2q15_ne_:
|
||||
; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
|
||||
|
||||
define { i32 } @compare_v2q15_ne_(i32 %a0.coerce, i32 %a1.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%cmp = icmp ne <2 x i16> %0, %1
|
||||
%sext = sext <2 x i1> %cmp to <2 x i16>
|
||||
%2 = bitcast <2 x i16> %sext to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: compare_v2q15_gt_:
|
||||
; CHECK: cmp.le.ph $4, $5
|
||||
; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
|
||||
|
||||
define { i32 } @compare_v2q15_gt_(i32 %a0.coerce, i32 %a1.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%cmp = icmp sgt <2 x i16> %0, %1
|
||||
%sext = sext <2 x i1> %cmp to <2 x i16>
|
||||
%2 = bitcast <2 x i16> %sext to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: compare_v2q15_ge_:
|
||||
; CHECK: cmp.lt.ph $4, $5
|
||||
; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
|
||||
|
||||
define { i32 } @compare_v2q15_ge_(i32 %a0.coerce, i32 %a1.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%cmp = icmp sge <2 x i16> %0, %1
|
||||
%sext = sext <2 x i1> %cmp to <2 x i16>
|
||||
%2 = bitcast <2 x i16> %sext to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: compare_v4ui8_eq_:
|
||||
; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
|
||||
|
||||
define { i32 } @compare_v4ui8_eq_(i32 %a0.coerce, i32 %a1.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = bitcast i32 %a1.coerce to <4 x i8>
|
||||
%cmp = icmp eq <4 x i8> %0, %1
|
||||
%sext = sext <4 x i1> %cmp to <4 x i8>
|
||||
%2 = bitcast <4 x i8> %sext to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: compare_v4ui8_lt_:
|
||||
; CHECK: cmpu.lt.qb $4, $5
|
||||
; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
|
||||
|
||||
define { i32 } @compare_v4ui8_lt_(i32 %a0.coerce, i32 %a1.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = bitcast i32 %a1.coerce to <4 x i8>
|
||||
%cmp = icmp ult <4 x i8> %0, %1
|
||||
%sext = sext <4 x i1> %cmp to <4 x i8>
|
||||
%2 = bitcast <4 x i8> %sext to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: compare_v4ui8_le_:
|
||||
; CHECK: cmpu.le.qb $4, $5
|
||||
; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
|
||||
|
||||
define { i32 } @compare_v4ui8_le_(i32 %a0.coerce, i32 %a1.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = bitcast i32 %a1.coerce to <4 x i8>
|
||||
%cmp = icmp ule <4 x i8> %0, %1
|
||||
%sext = sext <4 x i1> %cmp to <4 x i8>
|
||||
%2 = bitcast <4 x i8> %sext to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: compare_v4ui8_ne_:
|
||||
; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
|
||||
|
||||
define { i32 } @compare_v4ui8_ne_(i32 %a0.coerce, i32 %a1.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = bitcast i32 %a1.coerce to <4 x i8>
|
||||
%cmp = icmp ne <4 x i8> %0, %1
|
||||
%sext = sext <4 x i1> %cmp to <4 x i8>
|
||||
%2 = bitcast <4 x i8> %sext to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: compare_v4ui8_gt_:
|
||||
; CHECK: cmpu.le.qb $4, $5
|
||||
; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
|
||||
|
||||
define { i32 } @compare_v4ui8_gt_(i32 %a0.coerce, i32 %a1.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = bitcast i32 %a1.coerce to <4 x i8>
|
||||
%cmp = icmp ugt <4 x i8> %0, %1
|
||||
%sext = sext <4 x i1> %cmp to <4 x i8>
|
||||
%2 = bitcast <4 x i8> %sext to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: compare_v4ui8_ge_:
|
||||
; CHECK: cmpu.lt.qb $4, $5
|
||||
; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
|
||||
|
||||
define { i32 } @compare_v4ui8_ge_(i32 %a0.coerce, i32 %a1.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = bitcast i32 %a1.coerce to <4 x i8>
|
||||
%cmp = icmp uge <4 x i8> %0, %1
|
||||
%sext = sext <4 x i1> %cmp to <4 x i8>
|
||||
%2 = bitcast <4 x i8> %sext to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: compare_v2ui16_lt_:
|
||||
; CHECK-NOT: cmp
|
||||
; CHECK-NOT: pick
|
||||
|
||||
define { i32 } @compare_v2ui16_lt_(i32 %a0.coerce, i32 %a1.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%cmp = icmp ult <2 x i16> %0, %1
|
||||
%sext = sext <2 x i1> %cmp to <2 x i16>
|
||||
%2 = bitcast <2 x i16> %sext to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: compare_v2ui16_le_:
|
||||
; CHECK-NOT: cmp
|
||||
; CHECK-NOT: pick
|
||||
|
||||
define { i32 } @compare_v2ui16_le_(i32 %a0.coerce, i32 %a1.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%cmp = icmp ule <2 x i16> %0, %1
|
||||
%sext = sext <2 x i1> %cmp to <2 x i16>
|
||||
%2 = bitcast <2 x i16> %sext to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: compare_v2ui16_gt_:
|
||||
; CHECK-NOT: cmp
|
||||
; CHECK-NOT: pick
|
||||
|
||||
define { i32 } @compare_v2ui16_gt_(i32 %a0.coerce, i32 %a1.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%cmp = icmp ugt <2 x i16> %0, %1
|
||||
%sext = sext <2 x i1> %cmp to <2 x i16>
|
||||
%2 = bitcast <2 x i16> %sext to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: compare_v2ui16_ge_:
|
||||
; CHECK-NOT: cmp
|
||||
; CHECK-NOT: pick
|
||||
|
||||
define { i32 } @compare_v2ui16_ge_(i32 %a0.coerce, i32 %a1.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%cmp = icmp uge <2 x i16> %0, %1
|
||||
%sext = sext <2 x i1> %cmp to <2 x i16>
|
||||
%2 = bitcast <2 x i16> %sext to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: compare_v4i8_lt_:
|
||||
; CHECK-NOT: cmp
|
||||
; CHECK-NOT: pick
|
||||
|
||||
define { i32 } @compare_v4i8_lt_(i32 %a0.coerce, i32 %a1.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = bitcast i32 %a1.coerce to <4 x i8>
|
||||
%cmp = icmp slt <4 x i8> %0, %1
|
||||
%sext = sext <4 x i1> %cmp to <4 x i8>
|
||||
%2 = bitcast <4 x i8> %sext to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: compare_v4i8_le_:
|
||||
; CHECK-NOT: cmp
|
||||
; CHECK-NOT: pick
|
||||
|
||||
define { i32 } @compare_v4i8_le_(i32 %a0.coerce, i32 %a1.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = bitcast i32 %a1.coerce to <4 x i8>
|
||||
%cmp = icmp sle <4 x i8> %0, %1
|
||||
%sext = sext <4 x i1> %cmp to <4 x i8>
|
||||
%2 = bitcast <4 x i8> %sext to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: compare_v4i8_gt_:
|
||||
; CHECK-NOT: cmp
|
||||
; CHECK-NOT: pick
|
||||
|
||||
define { i32 } @compare_v4i8_gt_(i32 %a0.coerce, i32 %a1.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = bitcast i32 %a1.coerce to <4 x i8>
|
||||
%cmp = icmp sgt <4 x i8> %0, %1
|
||||
%sext = sext <4 x i1> %cmp to <4 x i8>
|
||||
%2 = bitcast <4 x i8> %sext to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
; CHECK: compare_v4i8_ge_:
|
||||
; CHECK-NOT: cmp
|
||||
; CHECK-NOT: pick
|
||||
|
||||
define { i32 } @compare_v4i8_ge_(i32 %a0.coerce, i32 %a1.coerce) {
|
||||
entry:
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = bitcast i32 %a1.coerce to <4 x i8>
|
||||
%cmp = icmp sge <4 x i8> %0, %1
|
||||
%sext = sext <4 x i1> %cmp to <4 x i8>
|
||||
%2 = bitcast <4 x i8> %sext to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user