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AMDGPU: Remove legacy bfe intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299372 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
parent
211802721c
commit
cd7c9c3178
@ -213,10 +213,6 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
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// This is totally unsupported, just custom lower to produce an error.
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
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// We need to custom lower some of the intrinsics
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
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setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
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// Library functions. These default to Expand, but we have instructions
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// for them.
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setOperationAction(ISD::FCEIL, MVT::f32, Legal);
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@ -912,7 +908,6 @@ SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
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case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
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case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
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case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
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case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
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case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
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case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
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case ISD::FREM: return LowerFREM(Op, DAG);
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@ -1009,28 +1004,6 @@ SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
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return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Args);
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}
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SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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SelectionDAG &DAG) const {
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unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
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SDLoc DL(Op);
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EVT VT = Op.getValueType();
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switch (IntrinsicID) {
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default: return Op;
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case AMDGPUIntrinsic::AMDGPU_bfe_i32:
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return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
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Op.getOperand(1),
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Op.getOperand(2),
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Op.getOperand(3));
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case AMDGPUIntrinsic::AMDGPU_bfe_u32:
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return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
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Op.getOperand(1),
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Op.getOperand(2),
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Op.getOperand(3));
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}
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}
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/// \brief Generate Min/Max node
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SDValue AMDGPUTargetLowering::combineFMinMaxLegacy(const SDLoc &DL, EVT VT,
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SDValue LHS, SDValue RHS,
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@ -39,7 +39,6 @@ protected:
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SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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/// \brief Split a vector store into multiple scalar stores.
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/// \returns The resulting chain.
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@ -14,10 +14,6 @@
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let TargetPrefix = "AMDGPU", isTarget = 1 in {
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def int_AMDGPU_kill : Intrinsic<[], [llvm_float_ty], []>;
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def int_AMDGPU_kilp : Intrinsic<[], [], []>;
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// Deprecated in favor of expanded bit operations
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def int_AMDGPU_bfe_i32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_AMDGPU_bfe_u32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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}
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include "SIIntrinsics.td"
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@ -226,6 +226,10 @@ R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
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// We need to custom lower some of the intrinsics
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setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
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setSchedulingPreference(Sched::Source);
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setTargetDAGCombine(ISD::FP_ROUND);
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@ -495,8 +499,7 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
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cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
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EVT VT = Op.getValueType();
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SDLoc DL(Op);
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switch(IntrinsicID) {
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default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
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switch (IntrinsicID) {
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case AMDGPUIntrinsic::r600_tex:
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case AMDGPUIntrinsic::r600_texc: {
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unsigned TextureOp;
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@ -604,6 +607,8 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
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case Intrinsic::r600_recipsqrt_clamped:
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return DAG.getNode(AMDGPUISD::RSQ_CLAMP, DL, VT, Op.getOperand(1));
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default:
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return Op;
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}
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// break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
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@ -189,12 +189,16 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2f16, Custom);
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setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
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setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
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setOperationAction(ISD::INTRINSIC_VOID, MVT::v2i16, Custom);
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setOperationAction(ISD::INTRINSIC_VOID, MVT::v2f16, Custom);
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2f16, Custom);
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setOperationAction(ISD::BRCOND, MVT::Other, Custom);
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setOperationAction(ISD::BR_CC, MVT::i1, Expand);
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@ -2945,7 +2949,7 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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return DAG.getNode(ISD::BITCAST, DL, VT, Node);
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}
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default:
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return AMDGPUTargetLowering::LowerOperation(Op, DAG);
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return Op;
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}
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}
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@ -3184,7 +3188,7 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
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return DAG.getNode(Opc, DL, Op->getVTList(), Ops);
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}
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default:
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return SDValue();
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return Op;
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}
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}
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@ -1,437 +0,0 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood -show-mc-encoding -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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declare i32 @llvm.AMDGPU.bfe.i32(i32, i32, i32) nounwind readnone
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; FUNC-LABEL: {{^}}bfe_i32_arg_arg_arg:
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; SI: v_bfe_i32
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; EG: BFE_INT
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; EG: encoding: [{{[x0-9a-f]+,[x0-9a-f]+,[x0-9a-f]+,[x0-9a-f]+,[x0-9a-f]+}},0xac
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define amdgpu_kernel void @bfe_i32_arg_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind {
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%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %src0, i32 %src1, i32 %src1) nounwind readnone
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}bfe_i32_arg_arg_imm:
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; SI: v_bfe_i32
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; EG: BFE_INT
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define amdgpu_kernel void @bfe_i32_arg_arg_imm(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
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%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %src0, i32 %src1, i32 123) nounwind readnone
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}bfe_i32_arg_imm_arg:
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; SI: v_bfe_i32
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; EG: BFE_INT
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define amdgpu_kernel void @bfe_i32_arg_imm_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src2) nounwind {
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%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %src0, i32 123, i32 %src2) nounwind readnone
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}bfe_i32_imm_arg_arg:
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; SI: v_bfe_i32
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; EG: BFE_INT
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define amdgpu_kernel void @bfe_i32_imm_arg_arg(i32 addrspace(1)* %out, i32 %src1, i32 %src2) nounwind {
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%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 123, i32 %src1, i32 %src2) nounwind readnone
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_bfe_print_arg:
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; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 2, 8
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define amdgpu_kernel void @v_bfe_print_arg(i32 addrspace(1)* %out, i32 addrspace(1)* %src0) nounwind {
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%load = load i32, i32 addrspace(1)* %src0, align 4
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%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %load, i32 2, i32 8) nounwind readnone
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}bfe_i32_arg_0_width_reg_offset:
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; SI-NOT: {{[^@]}}bfe
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; SI: s_endpgm
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; EG-NOT: BFE
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define amdgpu_kernel void @bfe_i32_arg_0_width_reg_offset(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
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%bfe_u32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %src0, i32 %src1, i32 0) nounwind readnone
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store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}bfe_i32_arg_0_width_imm_offset:
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; SI-NOT: {{[^@]}}bfe
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; SI: s_endpgm
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; EG-NOT: BFE
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define amdgpu_kernel void @bfe_i32_arg_0_width_imm_offset(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
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%bfe_u32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %src0, i32 8, i32 0) nounwind readnone
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store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}bfe_i32_test_6:
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; SI: v_lshlrev_b32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}}
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; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
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; SI: s_endpgm
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define amdgpu_kernel void @bfe_i32_test_6(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%x = load i32, i32 addrspace(1)* %in, align 4
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%shl = shl i32 %x, 31
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%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shl, i32 1, i32 31)
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store i32 %bfe, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}bfe_i32_test_7:
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; SI-NOT: shl
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; SI-NOT: {{[^@]}}bfe
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; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
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; SI: buffer_store_dword [[VREG]],
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; SI: s_endpgm
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define amdgpu_kernel void @bfe_i32_test_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%x = load i32, i32 addrspace(1)* %in, align 4
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%shl = shl i32 %x, 31
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%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shl, i32 0, i32 31)
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store i32 %bfe, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}bfe_i32_test_8:
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; SI: buffer_load_dword
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; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 1
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; SI: s_endpgm
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define amdgpu_kernel void @bfe_i32_test_8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%x = load i32, i32 addrspace(1)* %in, align 4
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%shl = shl i32 %x, 31
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%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shl, i32 31, i32 1)
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store i32 %bfe, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}bfe_i32_test_9:
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; SI-NOT: {{[^@]}}bfe
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; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}}
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; SI-NOT: {{[^@]}}bfe
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; SI: s_endpgm
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define amdgpu_kernel void @bfe_i32_test_9(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%x = load i32, i32 addrspace(1)* %in, align 4
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%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 31, i32 1)
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store i32 %bfe, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}bfe_i32_test_10:
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; SI-NOT: {{[^@]}}bfe
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; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
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; SI-NOT: {{[^@]}}bfe
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; SI: s_endpgm
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define amdgpu_kernel void @bfe_i32_test_10(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%x = load i32, i32 addrspace(1)* %in, align 4
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%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 1, i32 31)
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store i32 %bfe, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}bfe_i32_test_11:
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; SI-NOT: {{[^@]}}bfe
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; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 8, v{{[0-9]+}}
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; SI-NOT: {{[^@]}}bfe
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; SI: s_endpgm
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define amdgpu_kernel void @bfe_i32_test_11(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%x = load i32, i32 addrspace(1)* %in, align 4
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%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 8, i32 24)
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store i32 %bfe, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}bfe_i32_test_12:
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; SI-NOT: {{[^@]}}bfe
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; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 24, v{{[0-9]+}}
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; SI-NOT: {{[^@]}}bfe
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; SI: s_endpgm
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define amdgpu_kernel void @bfe_i32_test_12(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%x = load i32, i32 addrspace(1)* %in, align 4
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%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 24, i32 8)
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store i32 %bfe, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}bfe_i32_test_13:
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; SI: v_ashrrev_i32_e32 {{v[0-9]+}}, 31, {{v[0-9]+}}
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; SI-NOT: {{[^@]}}bfe
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; SI: s_endpgm
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define amdgpu_kernel void @bfe_i32_test_13(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%x = load i32, i32 addrspace(1)* %in, align 4
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%shl = ashr i32 %x, 31
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%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shl, i32 31, i32 1)
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store i32 %bfe, i32 addrspace(1)* %out, align 4 ret void
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}
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; FUNC-LABEL: {{^}}bfe_i32_test_14:
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; SI-NOT: lshr
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; SI-NOT: {{[^@]}}bfe
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; SI: s_endpgm
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define amdgpu_kernel void @bfe_i32_test_14(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%x = load i32, i32 addrspace(1)* %in, align 4
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%shl = lshr i32 %x, 31
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%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shl, i32 31, i32 1)
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store i32 %bfe, i32 addrspace(1)* %out, align 4 ret void
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}
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; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_0:
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; SI-NOT: {{[^@]}}bfe
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; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
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; SI: buffer_store_dword [[VREG]],
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; SI: s_endpgm
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; EG-NOT: BFE
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define amdgpu_kernel void @bfe_i32_constant_fold_test_0(i32 addrspace(1)* %out) nounwind {
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%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 0, i32 0, i32 0) nounwind readnone
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_1:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_1(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 12334, i32 0, i32 0) nounwind readnone
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_2:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_2(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 0, i32 0, i32 1) nounwind readnone
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_3:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_3(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 1, i32 0, i32 1) nounwind readnone
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_4:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_4(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 4294967295, i32 0, i32 1) nounwind readnone
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_5:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_5(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 128, i32 7, i32 1) nounwind readnone
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_6:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0xffffff80
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_6(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 128, i32 0, i32 8) nounwind readnone
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_7:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0x7f
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_7(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 127, i32 0, i32 8) nounwind readnone
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_8:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_8(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 127, i32 6, i32 8) nounwind readnone
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_9:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_9(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 65536, i32 16, i32 8) nounwind readnone
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_10:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_10(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 65535, i32 16, i32 16) nounwind readnone
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_11:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -6
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_11(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 160, i32 4, i32 4) nounwind readnone
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_12:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_12(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 160, i32 31, i32 1) nounwind readnone
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_13:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_13(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 131070, i32 16, i32 16) nounwind readnone
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_14:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 40
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_14(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 160, i32 2, i32 30) nounwind readnone
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_15:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 10
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_15(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 160, i32 4, i32 28) nounwind readnone
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_16:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_16(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 4294967295, i32 1, i32 7) nounwind readnone
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_17:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0x7f
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_17(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 255, i32 1, i32 31) nounwind readnone
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_18:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_i32_constant_fold_test_18(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 255, i32 31, i32 1) nounwind readnone
|
||||
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_sext_in_reg_i24:
|
||||
; SI: buffer_load_dword [[LOAD:v[0-9]+]],
|
||||
; SI-NOT: v_lshl
|
||||
; SI-NOT: v_ashr
|
||||
; SI: v_bfe_i32 [[BFE:v[0-9]+]], [[LOAD]], 0, 24
|
||||
; SI: buffer_store_dword [[BFE]],
|
||||
define amdgpu_kernel void @bfe_sext_in_reg_i24(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 0, i32 24)
|
||||
%shl = shl i32 %bfe, 8
|
||||
%ashr = ashr i32 %shl, 8
|
||||
store i32 %ashr, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @simplify_demanded_bfe_sdiv
|
||||
; SI: buffer_load_dword [[LOAD:v[0-9]+]]
|
||||
; SI: v_bfe_i32 [[BFE:v[0-9]+]], [[LOAD]], 1, 16
|
||||
; SI: v_lshrrev_b32_e32 [[TMP0:v[0-9]+]], 31, [[BFE]]
|
||||
; SI: v_add_i32_e32 [[TMP1:v[0-9]+]], vcc, [[TMP0]], [[BFE]]
|
||||
; SI: v_ashrrev_i32_e32 [[TMP2:v[0-9]+]], 1, [[TMP1]]
|
||||
; SI: buffer_store_dword [[TMP2]]
|
||||
define amdgpu_kernel void @simplify_demanded_bfe_sdiv(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
|
||||
%src = load i32, i32 addrspace(1)* %in, align 4
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %src, i32 1, i32 16) nounwind readnone
|
||||
%div = sdiv i32 %bfe, 2
|
||||
store i32 %div, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
@ -1,631 +0,0 @@
|
||||
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC -check-prefix=GCN %s
|
||||
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC -check-prefix=GCN %s
|
||||
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC -check-prefix=GCN %s
|
||||
; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
|
||||
|
||||
declare i32 @llvm.AMDGPU.bfe.u32(i32, i32, i32) nounwind readnone
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_arg_arg_arg:
|
||||
; SI: v_bfe_u32
|
||||
; EG: BFE_UINT
|
||||
define amdgpu_kernel void @bfe_u32_arg_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind {
|
||||
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %src0, i32 %src1, i32 %src1) nounwind readnone
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_arg_arg_imm:
|
||||
; SI: v_bfe_u32
|
||||
; EG: BFE_UINT
|
||||
define amdgpu_kernel void @bfe_u32_arg_arg_imm(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
|
||||
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %src0, i32 %src1, i32 123) nounwind readnone
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_arg_imm_arg:
|
||||
; SI: v_bfe_u32
|
||||
; EG: BFE_UINT
|
||||
define amdgpu_kernel void @bfe_u32_arg_imm_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src2) nounwind {
|
||||
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %src0, i32 123, i32 %src2) nounwind readnone
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_imm_arg_arg:
|
||||
; SI: v_bfe_u32
|
||||
; EG: BFE_UINT
|
||||
define amdgpu_kernel void @bfe_u32_imm_arg_arg(i32 addrspace(1)* %out, i32 %src1, i32 %src2) nounwind {
|
||||
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 123, i32 %src1, i32 %src2) nounwind readnone
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_arg_0_width_reg_offset:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_u32_arg_0_width_reg_offset(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
|
||||
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %src0, i32 %src1, i32 0) nounwind readnone
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_arg_0_width_imm_offset:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_u32_arg_0_width_imm_offset(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
|
||||
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %src0, i32 8, i32 0) nounwind readnone
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_zextload_i8:
|
||||
; SI: buffer_load_ubyte
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @bfe_u32_zextload_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) nounwind {
|
||||
%load = load i8, i8 addrspace(1)* %in
|
||||
%ext = zext i8 %load to i32
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 0, i32 8)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_zext_in_reg_i8:
|
||||
; GCN: buffer_load_dword
|
||||
; SI: v_add_i32
|
||||
; SI-NEXT: v_and_b32_e32
|
||||
; FIXME: Should be using s_add_i32
|
||||
; VI: v_add_i32
|
||||
; VI-NEXT: v_and_b32_e32
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @bfe_u32_zext_in_reg_i8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
|
||||
%load = load i32, i32 addrspace(1)* %in, align 4
|
||||
%add = add i32 %load, 1
|
||||
%ext = and i32 %add, 255
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 0, i32 8)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_zext_in_reg_i16:
|
||||
; SI: buffer_load_dword
|
||||
; SI: v_add_i32
|
||||
; SI-NEXT: v_and_b32_e32
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @bfe_u32_zext_in_reg_i16(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
|
||||
%load = load i32, i32 addrspace(1)* %in, align 4
|
||||
%add = add i32 %load, 1
|
||||
%ext = and i32 %add, 65535
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 0, i32 16)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_zext_in_reg_i8_offset_1:
|
||||
; SI: buffer_load_dword
|
||||
; SI: v_add_i32
|
||||
; SI: bfe
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @bfe_u32_zext_in_reg_i8_offset_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
|
||||
%load = load i32, i32 addrspace(1)* %in, align 4
|
||||
%add = add i32 %load, 1
|
||||
%ext = and i32 %add, 255
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 1, i32 8)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_zext_in_reg_i8_offset_3:
|
||||
; SI: buffer_load_dword
|
||||
; SI: v_add_i32
|
||||
; SI-NEXT: v_and_b32_e32 {{v[0-9]+}}, 0xf8
|
||||
; SI-NEXT: bfe
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @bfe_u32_zext_in_reg_i8_offset_3(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
|
||||
%load = load i32, i32 addrspace(1)* %in, align 4
|
||||
%add = add i32 %load, 1
|
||||
%ext = and i32 %add, 255
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 3, i32 8)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_zext_in_reg_i8_offset_7:
|
||||
; SI: buffer_load_dword
|
||||
; SI: v_add_i32
|
||||
; SI-NEXT: v_and_b32_e32 {{v[0-9]+}}, 0x80
|
||||
; SI-NEXT: bfe
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @bfe_u32_zext_in_reg_i8_offset_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
|
||||
%load = load i32, i32 addrspace(1)* %in, align 4
|
||||
%add = add i32 %load, 1
|
||||
%ext = and i32 %add, 255
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 7, i32 8)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_zext_in_reg_i16_offset_8:
|
||||
; SI: buffer_load_dword
|
||||
; SI: v_add_i32
|
||||
; SI-NEXT: bfe
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @bfe_u32_zext_in_reg_i16_offset_8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
|
||||
%load = load i32, i32 addrspace(1)* %in, align 4
|
||||
%add = add i32 %load, 1
|
||||
%ext = and i32 %add, 65535
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 8, i32 8)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_test_1:
|
||||
; SI: buffer_load_dword
|
||||
; SI: v_and_b32_e32 {{v[0-9]+}}, 1, {{v[0-9]+}}
|
||||
; SI: s_endpgm
|
||||
; EG: AND_INT T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}, 1,
|
||||
define amdgpu_kernel void @bfe_u32_test_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 0, i32 1)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_u32_test_2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%shl = shl i32 %x, 31
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 0, i32 8)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @bfe_u32_test_3(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%shl = shl i32 %x, 31
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 0, i32 1)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_test_4:
|
||||
; SI-NOT: lshl
|
||||
; SI-NOT: shr
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @bfe_u32_test_4(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%shl = shl i32 %x, 31
|
||||
%shr = lshr i32 %shl, 31
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shr, i32 31, i32 1)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_test_5:
|
||||
; SI: buffer_load_dword
|
||||
; SI-NOT: lshl
|
||||
; SI-NOT: shr
|
||||
; SI: v_bfe_i32 {{v[0-9]+}}, {{v[0-9]+}}, 0, 1
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @bfe_u32_test_5(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%shl = shl i32 %x, 31
|
||||
%shr = ashr i32 %shl, 31
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shr, i32 0, i32 1)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_test_6:
|
||||
; SI: v_lshlrev_b32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}}
|
||||
; SI: v_lshrrev_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @bfe_u32_test_6(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%shl = shl i32 %x, 31
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 1, i32 31)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_test_7:
|
||||
; SI: v_lshlrev_b32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}}
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @bfe_u32_test_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%shl = shl i32 %x, 31
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 0, i32 31)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_test_8:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_and_b32_e32 {{v[0-9]+}}, 1, {{v[0-9]+}}
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @bfe_u32_test_8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%shl = shl i32 %x, 31
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 31, i32 1)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_test_9:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_lshrrev_b32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}}
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @bfe_u32_test_9(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 31, i32 1)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_test_10:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_lshrrev_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @bfe_u32_test_10(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 1, i32 31)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_test_11:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_lshrrev_b32_e32 v{{[0-9]+}}, 8, v{{[0-9]+}}
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @bfe_u32_test_11(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 8, i32 24)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_test_12:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_lshrrev_b32_e32 v{{[0-9]+}}, 24, v{{[0-9]+}}
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @bfe_u32_test_12(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 24, i32 8)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_test_13:
|
||||
; V_ASHRREV_U32_e32 {{v[0-9]+}}, 31, {{v[0-9]+}}
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @bfe_u32_test_13(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%shl = ashr i32 %x, 31
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 31, i32 1)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4 ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_test_14:
|
||||
; SI-NOT: lshr
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @bfe_u32_test_14(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%shl = lshr i32 %x, 31
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 31, i32 1)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4 ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_0:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_u32_constant_fold_test_0(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 0, i32 0, i32 0) nounwind readnone
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_1:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_u32_constant_fold_test_1(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 12334, i32 0, i32 0) nounwind readnone
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_2:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_u32_constant_fold_test_2(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 0, i32 0, i32 1) nounwind readnone
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_3:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_u32_constant_fold_test_3(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 1, i32 0, i32 1) nounwind readnone
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_4:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_u32_constant_fold_test_4(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 4294967295, i32 0, i32 1) nounwind readnone
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_5:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_u32_constant_fold_test_5(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 128, i32 7, i32 1) nounwind readnone
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_6:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0x80
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_u32_constant_fold_test_6(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 128, i32 0, i32 8) nounwind readnone
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_7:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0x7f
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_u32_constant_fold_test_7(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 127, i32 0, i32 8) nounwind readnone
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_8:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_u32_constant_fold_test_8(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 127, i32 6, i32 8) nounwind readnone
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_9:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_u32_constant_fold_test_9(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 65536, i32 16, i32 8) nounwind readnone
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_10:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_u32_constant_fold_test_10(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 65535, i32 16, i32 16) nounwind readnone
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_11:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 10
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_u32_constant_fold_test_11(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 160, i32 4, i32 4) nounwind readnone
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_12:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_u32_constant_fold_test_12(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 160, i32 31, i32 1) nounwind readnone
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_13:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_u32_constant_fold_test_13(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 131070, i32 16, i32 16) nounwind readnone
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_14:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 40
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_u32_constant_fold_test_14(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 160, i32 2, i32 30) nounwind readnone
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_15:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 10
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_u32_constant_fold_test_15(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 160, i32 4, i32 28) nounwind readnone
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_16:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0x7f
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_u32_constant_fold_test_16(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 4294967295, i32 1, i32 7) nounwind readnone
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_17:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0x7f
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_u32_constant_fold_test_17(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 255, i32 1, i32 31) nounwind readnone
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_18:
|
||||
; SI-NOT: {{[^@]}}bfe
|
||||
; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
|
||||
; SI: buffer_store_dword [[VREG]],
|
||||
; SI: s_endpgm
|
||||
; EG-NOT: BFE
|
||||
define amdgpu_kernel void @bfe_u32_constant_fold_test_18(i32 addrspace(1)* %out) nounwind {
|
||||
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 255, i32 31, i32 1) nounwind readnone
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Make sure that SimplifyDemandedBits doesn't cause the and to be
|
||||
; reduced to the bits demanded by the bfe.
|
||||
|
||||
; XXX: The operand to v_bfe_u32 could also just directly be the load register.
|
||||
; FUNC-LABEL: {{^}}simplify_bfe_u32_multi_use_arg:
|
||||
; SI: buffer_load_dword [[ARG:v[0-9]+]]
|
||||
; SI: v_and_b32_e32 [[AND:v[0-9]+]], 63, [[ARG]]
|
||||
; SI: v_bfe_u32 [[BFE:v[0-9]+]], [[AND]], 2, 2
|
||||
; SI-DAG: buffer_store_dword [[AND]]
|
||||
; SI-DAG: buffer_store_dword [[BFE]]
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @simplify_bfe_u32_multi_use_arg(i32 addrspace(1)* %out0,
|
||||
i32 addrspace(1)* %out1,
|
||||
i32 addrspace(1)* %in) nounwind {
|
||||
%src = load i32, i32 addrspace(1)* %in, align 4
|
||||
%and = and i32 %src, 63
|
||||
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %and, i32 2, i32 2) nounwind readnone
|
||||
store i32 %bfe_u32, i32 addrspace(1)* %out0, align 4
|
||||
store i32 %and, i32 addrspace(1)* %out1, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}lshr_and:
|
||||
; SI: s_bfe_u32 {{s[0-9]+}}, {{s[0-9]+}}, 0x30006
|
||||
; SI: buffer_store_dword
|
||||
define amdgpu_kernel void @lshr_and(i32 addrspace(1)* %out, i32 %a) nounwind {
|
||||
%b = lshr i32 %a, 6
|
||||
%c = and i32 %b, 7
|
||||
store i32 %c, i32 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}v_lshr_and:
|
||||
; SI: v_bfe_u32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}, 3
|
||||
; SI: buffer_store_dword
|
||||
define amdgpu_kernel void @v_lshr_and(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
|
||||
%c = lshr i32 %a, %b
|
||||
%d = and i32 %c, 7
|
||||
store i32 %d, i32 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}and_lshr:
|
||||
; SI: s_bfe_u32 {{s[0-9]+}}, {{s[0-9]+}}, 0x30006
|
||||
; SI: buffer_store_dword
|
||||
define amdgpu_kernel void @and_lshr(i32 addrspace(1)* %out, i32 %a) nounwind {
|
||||
%b = and i32 %a, 448
|
||||
%c = lshr i32 %b, 6
|
||||
store i32 %c, i32 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}and_lshr2:
|
||||
; SI: s_bfe_u32 {{s[0-9]+}}, {{s[0-9]+}}, 0x30006
|
||||
; SI: buffer_store_dword
|
||||
define amdgpu_kernel void @and_lshr2(i32 addrspace(1)* %out, i32 %a) nounwind {
|
||||
%b = and i32 %a, 511
|
||||
%c = lshr i32 %b, 6
|
||||
store i32 %c, i32 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}shl_lshr:
|
||||
; SI: s_bfe_u32 {{s[0-9]+}}, {{s[0-9]+}}, 0x150002
|
||||
; SI: buffer_store_dword
|
||||
define amdgpu_kernel void @shl_lshr(i32 addrspace(1)* %out, i32 %a) nounwind {
|
||||
%b = shl i32 %a, 9
|
||||
%c = lshr i32 %b, 11
|
||||
store i32 %c, i32 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
@ -407,6 +407,149 @@ define amdgpu_kernel void @simplify_demanded_bfe_sdiv(i32 addrspace(1)* %out, i3
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}bfe_0_width:
|
||||
; GCN-NOT: {{[^@]}}bfe
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @bfe_0_width(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {
|
||||
%load = load i32, i32 addrspace(1)* %ptr, align 4
|
||||
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %load, i32 8, i32 0)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}bfe_8_bfe_8:
|
||||
; GCN: v_bfe_i32
|
||||
; GCN-NOT: {{[^@]}}bfe
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @bfe_8_bfe_8(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {
|
||||
%load = load i32, i32 addrspace(1)* %ptr, align 4
|
||||
%bfe0 = call i32 @llvm.amdgcn.sbfe.i32(i32 %load, i32 0, i32 8)
|
||||
%bfe1 = call i32 @llvm.amdgcn.sbfe.i32(i32 %bfe0, i32 0, i32 8)
|
||||
store i32 %bfe1, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}bfe_8_bfe_16:
|
||||
; GCN: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 8
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @bfe_8_bfe_16(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {
|
||||
%load = load i32, i32 addrspace(1)* %ptr, align 4
|
||||
%bfe0 = call i32 @llvm.amdgcn.sbfe.i32(i32 %load, i32 0, i32 8)
|
||||
%bfe1 = call i32 @llvm.amdgcn.sbfe.i32(i32 %bfe0, i32 0, i32 16)
|
||||
store i32 %bfe1, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; This really should be folded into 1
|
||||
; GCN-LABEL: {{^}}bfe_16_bfe_8:
|
||||
; GCN: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 8
|
||||
; GCN-NOT: {{[^@]}}bfe
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @bfe_16_bfe_8(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {
|
||||
%load = load i32, i32 addrspace(1)* %ptr, align 4
|
||||
%bfe0 = call i32 @llvm.amdgcn.sbfe.i32(i32 %load, i32 0, i32 16)
|
||||
%bfe1 = call i32 @llvm.amdgcn.sbfe.i32(i32 %bfe0, i32 0, i32 8)
|
||||
store i32 %bfe1, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Make sure there isn't a redundant BFE
|
||||
; GCN-LABEL: {{^}}sext_in_reg_i8_to_i32_bfe:
|
||||
; GCN: s_sext_i32_i8 s{{[0-9]+}}, s{{[0-9]+}}
|
||||
; GCN-NOT: {{[^@]}}bfe
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @sext_in_reg_i8_to_i32_bfe(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
|
||||
%c = add i32 %a, %b ; add to prevent folding into extload
|
||||
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %c, i32 0, i32 8)
|
||||
%shl = shl i32 %bfe, 24
|
||||
%ashr = ashr i32 %shl, 24
|
||||
store i32 %ashr, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sext_in_reg_i8_to_i32_bfe_wrong:
|
||||
define amdgpu_kernel void @sext_in_reg_i8_to_i32_bfe_wrong(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
|
||||
%c = add i32 %a, %b ; add to prevent folding into extload
|
||||
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %c, i32 8, i32 0)
|
||||
%shl = shl i32 %bfe, 24
|
||||
%ashr = ashr i32 %shl, 24
|
||||
store i32 %ashr, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sextload_i8_to_i32_bfe:
|
||||
; GCN: buffer_load_sbyte
|
||||
; GCN-NOT: {{[^@]}}bfe
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @sextload_i8_to_i32_bfe(i32 addrspace(1)* %out, i8 addrspace(1)* %ptr) #0 {
|
||||
%load = load i8, i8 addrspace(1)* %ptr, align 1
|
||||
%sext = sext i8 %load to i32
|
||||
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %sext, i32 0, i32 8)
|
||||
%shl = shl i32 %bfe, 24
|
||||
%ashr = ashr i32 %shl, 24
|
||||
store i32 %ashr, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN: .text
|
||||
; GCN-LABEL: {{^}}sextload_i8_to_i32_bfe_0:{{.*$}}
|
||||
; GCN-NOT: {{[^@]}}bfe
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @sextload_i8_to_i32_bfe_0(i32 addrspace(1)* %out, i8 addrspace(1)* %ptr) #0 {
|
||||
%load = load i8, i8 addrspace(1)* %ptr, align 1
|
||||
%sext = sext i8 %load to i32
|
||||
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %sext, i32 8, i32 0)
|
||||
%shl = shl i32 %bfe, 24
|
||||
%ashr = ashr i32 %shl, 24
|
||||
store i32 %ashr, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sext_in_reg_i1_bfe_offset_0:
|
||||
; GCN-NOT: shr
|
||||
; GCN-NOT: shl
|
||||
; GCN: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 1
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @sext_in_reg_i1_bfe_offset_0(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%shl = shl i32 %x, 31
|
||||
%shr = ashr i32 %shl, 31
|
||||
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %shr, i32 0, i32 1)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sext_in_reg_i1_bfe_offset_1:
|
||||
; GCN: buffer_load_dword
|
||||
; GCN-NOT: shl
|
||||
; GCN-NOT: shr
|
||||
; GCN: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 1, 1
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @sext_in_reg_i1_bfe_offset_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%shl = shl i32 %x, 30
|
||||
%shr = ashr i32 %shl, 30
|
||||
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %shr, i32 1, i32 1)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sext_in_reg_i2_bfe_offset_1:
|
||||
; GCN: buffer_load_dword
|
||||
; GCN-NOT: v_lshl
|
||||
; GCN-NOT: v_ashr
|
||||
; GCN: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 2
|
||||
; GCN: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 1, 2
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @sext_in_reg_i2_bfe_offset_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%shl = shl i32 %x, 30
|
||||
%shr = ashr i32 %shl, 30
|
||||
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %shr, i32 1, i32 2)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
declare i32 @llvm.amdgcn.sbfe.i32(i32, i32, i32) #1
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
|
||||
@ -457,151 +457,6 @@ define amdgpu_kernel void @sext_in_reg_to_illegal_type(i16 addrspace(1)* nocaptu
|
||||
ret void
|
||||
}
|
||||
|
||||
declare i32 @llvm.AMDGPU.bfe.i32(i32, i32, i32) nounwind readnone
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_0_width:
|
||||
; GCN-NOT: {{[^@]}}bfe
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @bfe_0_width(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {
|
||||
%load = load i32, i32 addrspace(1)* %ptr, align 4
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %load, i32 8, i32 0) nounwind readnone
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_8_bfe_8:
|
||||
; GCN: v_bfe_i32
|
||||
; GCN-NOT: {{[^@]}}bfe
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @bfe_8_bfe_8(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {
|
||||
%load = load i32, i32 addrspace(1)* %ptr, align 4
|
||||
%bfe0 = call i32 @llvm.AMDGPU.bfe.i32(i32 %load, i32 0, i32 8) nounwind readnone
|
||||
%bfe1 = call i32 @llvm.AMDGPU.bfe.i32(i32 %bfe0, i32 0, i32 8) nounwind readnone
|
||||
store i32 %bfe1, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}bfe_8_bfe_16:
|
||||
; GCN: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 8
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @bfe_8_bfe_16(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {
|
||||
%load = load i32, i32 addrspace(1)* %ptr, align 4
|
||||
%bfe0 = call i32 @llvm.AMDGPU.bfe.i32(i32 %load, i32 0, i32 8) nounwind readnone
|
||||
%bfe1 = call i32 @llvm.AMDGPU.bfe.i32(i32 %bfe0, i32 0, i32 16) nounwind readnone
|
||||
store i32 %bfe1, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; This really should be folded into 1
|
||||
; FUNC-LABEL: {{^}}bfe_16_bfe_8:
|
||||
; GCN: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 8
|
||||
; GCN-NOT: {{[^@]}}bfe
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @bfe_16_bfe_8(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {
|
||||
%load = load i32, i32 addrspace(1)* %ptr, align 4
|
||||
%bfe0 = call i32 @llvm.AMDGPU.bfe.i32(i32 %load, i32 0, i32 16) nounwind readnone
|
||||
%bfe1 = call i32 @llvm.AMDGPU.bfe.i32(i32 %bfe0, i32 0, i32 8) nounwind readnone
|
||||
store i32 %bfe1, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Make sure there isn't a redundant BFE
|
||||
; FUNC-LABEL: {{^}}sext_in_reg_i8_to_i32_bfe:
|
||||
; GCN: s_sext_i32_i8 s{{[0-9]+}}, s{{[0-9]+}}
|
||||
; GCN-NOT: {{[^@]}}bfe
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @sext_in_reg_i8_to_i32_bfe(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
|
||||
%c = add i32 %a, %b ; add to prevent folding into extload
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %c, i32 0, i32 8) nounwind readnone
|
||||
%shl = shl i32 %bfe, 24
|
||||
%ashr = ashr i32 %shl, 24
|
||||
store i32 %ashr, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}sext_in_reg_i8_to_i32_bfe_wrong:
|
||||
define amdgpu_kernel void @sext_in_reg_i8_to_i32_bfe_wrong(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
|
||||
%c = add i32 %a, %b ; add to prevent folding into extload
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %c, i32 8, i32 0) nounwind readnone
|
||||
%shl = shl i32 %bfe, 24
|
||||
%ashr = ashr i32 %shl, 24
|
||||
store i32 %ashr, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}sextload_i8_to_i32_bfe:
|
||||
; GCN: buffer_load_sbyte
|
||||
; GCN-NOT: {{[^@]}}bfe
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @sextload_i8_to_i32_bfe(i32 addrspace(1)* %out, i8 addrspace(1)* %ptr) #0 {
|
||||
%load = load i8, i8 addrspace(1)* %ptr, align 1
|
||||
%sext = sext i8 %load to i32
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %sext, i32 0, i32 8) nounwind readnone
|
||||
%shl = shl i32 %bfe, 24
|
||||
%ashr = ashr i32 %shl, 24
|
||||
store i32 %ashr, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN: .text
|
||||
; FUNC-LABEL: {{^}}sextload_i8_to_i32_bfe_0:{{.*$}}
|
||||
; GCN-NOT: {{[^@]}}bfe
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @sextload_i8_to_i32_bfe_0(i32 addrspace(1)* %out, i8 addrspace(1)* %ptr) #0 {
|
||||
%load = load i8, i8 addrspace(1)* %ptr, align 1
|
||||
%sext = sext i8 %load to i32
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %sext, i32 8, i32 0) nounwind readnone
|
||||
%shl = shl i32 %bfe, 24
|
||||
%ashr = ashr i32 %shl, 24
|
||||
store i32 %ashr, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}sext_in_reg_i1_bfe_offset_0:
|
||||
; GCN-NOT: shr
|
||||
; GCN-NOT: shl
|
||||
; GCN: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 1
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @sext_in_reg_i1_bfe_offset_0(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%shl = shl i32 %x, 31
|
||||
%shr = ashr i32 %shl, 31
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shr, i32 0, i32 1)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}sext_in_reg_i1_bfe_offset_1:
|
||||
; GCN: buffer_load_dword
|
||||
; GCN-NOT: shl
|
||||
; GCN-NOT: shr
|
||||
; GCN: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 1, 1
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @sext_in_reg_i1_bfe_offset_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%shl = shl i32 %x, 30
|
||||
%shr = ashr i32 %shl, 30
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shr, i32 1, i32 1)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}sext_in_reg_i2_bfe_offset_1:
|
||||
; GCN: buffer_load_dword
|
||||
; GCN-NOT: v_lshl
|
||||
; GCN-NOT: v_ashr
|
||||
; GCN: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 2
|
||||
; GCN: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 1, 2
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @sext_in_reg_i2_bfe_offset_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
|
||||
%x = load i32, i32 addrspace(1)* %in, align 4
|
||||
%shl = shl i32 %x, 30
|
||||
%shr = ashr i32 %shl, 30
|
||||
%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shr, i32 1, i32 2)
|
||||
store i32 %bfe, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Make sure we propagate the VALUness to users of a moved scalar BFE.
|
||||
|
||||
; FUNC-LABEL: {{^}}v_sext_in_reg_i1_to_i64_move_use:
|
||||
|
||||
@ -9,11 +9,11 @@
|
||||
...
|
||||
---
|
||||
# Completely invalid code, but it checks that intrinsics round-trip properly.
|
||||
# CHECK: %0(s64) = COPY intrinsic(@llvm.AMDGPU.bfe.i32)
|
||||
# CHECK: %0(s64) = COPY intrinsic(@llvm.amdgcn.sbfe)
|
||||
name: use_intrin
|
||||
registers:
|
||||
- { id: 0, class: _ }
|
||||
body: |
|
||||
bb.0:
|
||||
%0(s64) = COPY intrinsic(@llvm.AMDGPU.bfe.i32)
|
||||
%0(s64) = COPY intrinsic(@llvm.amdgcn.sbfe.i32)
|
||||
...
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user