diff --git a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index 65f477642d7..1f70a3d32cb 100644
--- a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -1342,13 +1342,13 @@ static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn,
   case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register: {
     switch (Opc) {
     case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register:
-      TransferBytes = 3; break;
+      TransferBytes = 4; break;
     case AArch64::LD4LN_WB_H_fixed: case AArch64::LD4LN_WB_H_register:
-      TransferBytes = 6; break;
+      TransferBytes = 8; break;
     case AArch64::LD4LN_WB_S_fixed: case AArch64::LD4LN_WB_S_register:
-      TransferBytes = 12; break;
+      TransferBytes = 16; break;
     case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register:
-      TransferBytes = 24; break;
+      TransferBytes = 32; break;
     }
     IsLoad = true;
     NumVecs = 4;
diff --git a/test/MC/Disassembler/AArch64/neon-instructions.txt b/test/MC/Disassembler/AArch64/neon-instructions.txt
index f33c35bae30..23ee1eb38ab 100644
--- a/test/MC/Disassembler/AArch64/neon-instructions.txt
+++ b/test/MC/Disassembler/AArch64/neon-instructions.txt
@@ -2129,7 +2129,8 @@
 # CHECK: ld1 {v0.b}[9], [x0], #1
 # CHECK: ld2 {v15.h, v16.h}[7], [x15], #4
 # CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp], x3
-# CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #24
+# CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32
+# CHECK: ld4 {v0.h, v1.h, v2.h, v3.h}[7], [x0], x0
 # CHECK: st1 {v0.d}[1], [x0], #8
 # CHECK: st2 {v31.s, v0.s}[3], [sp], #8
 # CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15], #6
@@ -2138,6 +2139,7 @@
 0xef,0x59,0xff,0x4d
 0xff,0xb3,0xc3,0x4d
 0x00,0xa4,0xff,0x4d
+0x00,0x78,0xe0,0x4d
 0x00,0x84,0x9f,0x4d
 0xff,0x93,0xbf,0x4d
 0xef,0x79,0x9f,0x4d