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AlphaSchedule.td: 7bit-ize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114173 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -50,7 +50,7 @@ def s_ftoi : InstrItinClass;
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def s_itof : InstrItinClass;
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def s_pseudo : InstrItinClass;
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//Table 24 Instruction Class Latency in Cycles
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//Table 2-4 Instruction Class Latency in Cycles
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//modified some
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def Alpha21264Itineraries : ProcessorItineraries<
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