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Don't hardcode the %reg format in the streamer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132451 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -45,8 +45,8 @@ public:
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/// "MOV32ri") or empty if we can't resolve it.
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virtual StringRef getOpcodeName(unsigned Opcode) const;
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/// getRegName - Return the assembler register name.
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virtual StringRef getRegName(unsigned RegNo) const;
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/// printRegName - Print the assembler register name.
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virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
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unsigned getAvailableFeatures() const { return AvailableFeatures; }
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void setAvailableFeatures(unsigned Value) { AvailableFeatures = Value; }
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@ -825,7 +825,7 @@ void MCAsmStreamer::EmitRegisterName(int64_t Register) {
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if (InstPrinter) {
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const TargetAsmInfo &asmInfo = getContext().getTargetAsmInfo();
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unsigned LLVMRegister = asmInfo.getLLVMRegNum(Register, true);
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OS << '%' << InstPrinter->getRegName(LLVMRegister);
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InstPrinter->printRegName(OS, LLVMRegister);
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} else {
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OS << Register;
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}
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@ -1169,8 +1169,10 @@ void MCAsmStreamer::EmitPersonality(const MCSymbol *Personality) {
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}
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void MCAsmStreamer::EmitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset) {
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OS << "\t.setfp\t" << InstPrinter->getRegName(FpReg)
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<< ", " << InstPrinter->getRegName(SpReg);
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OS << "\t.setfp\t";
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InstPrinter->printRegName(OS, FpReg);
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OS << ", ";
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InstPrinter->printRegName(OS, SpReg);
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if (Offset)
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OS << ", #" << Offset;
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EmitEOL();
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@ -1189,10 +1191,12 @@ void MCAsmStreamer::EmitRegSave(const SmallVectorImpl<unsigned> &RegList,
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else
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OS << "\t.save\t{";
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OS << InstPrinter->getRegName(RegList[0]);
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InstPrinter->printRegName(OS, RegList[0]);
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for (unsigned i = 1, e = RegList.size(); i != e; ++i)
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OS << ", " << InstPrinter->getRegName(RegList[i]);
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for (unsigned i = 1, e = RegList.size(); i != e; ++i) {
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OS << ", ";
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InstPrinter->printRegName(OS, RegList[i]);
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}
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OS << "}";
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EmitEOL();
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@ -20,7 +20,6 @@ StringRef MCInstPrinter::getOpcodeName(unsigned Opcode) const {
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return "";
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}
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StringRef MCInstPrinter::getRegName(unsigned RegNo) const {
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void MCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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assert(0 && "Target should implement this");
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return "";
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}
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@ -29,8 +29,8 @@ StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
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return getInstructionName(Opcode);
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}
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StringRef ARMInstPrinter::getRegName(unsigned RegNo) const {
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return getRegisterName(RegNo);
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void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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OS << getRegisterName(RegNo);
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}
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void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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@ -28,7 +28,7 @@ public:
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virtual void printInst(const MCInst *MI, raw_ostream &O);
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virtual StringRef getOpcodeName(unsigned Opcode) const;
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virtual StringRef getRegName(unsigned RegNo) const;
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virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
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static const char *getInstructionName(unsigned Opcode);
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@ -26,8 +26,8 @@ StringRef PPCInstPrinter::getOpcodeName(unsigned Opcode) const {
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return getInstructionName(Opcode);
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}
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StringRef PPCInstPrinter::getRegName(unsigned RegNo) const {
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return getRegisterName(RegNo);
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void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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OS << getRegisterName(RegNo);
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}
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void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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@ -33,7 +33,7 @@ public:
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return SyntaxVariant == 1;
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}
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StringRef getRegName(unsigned RegNo) const;
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virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
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virtual void printInst(const MCInst *MI, raw_ostream &O);
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virtual StringRef getOpcodeName(unsigned Opcode) const;
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@ -41,8 +41,9 @@ X86ATTInstPrinter::X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI)
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&TM.getSubtarget<X86Subtarget>()));
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}
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StringRef X86ATTInstPrinter::getRegName(unsigned RegNo) const {
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return getRegisterName(RegNo);
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void X86ATTInstPrinter::printRegName(raw_ostream &OS,
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unsigned RegNo) const {
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OS << '%' << getRegisterName(RegNo);
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}
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void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) {
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@ -26,7 +26,7 @@ class X86ATTInstPrinter : public MCInstPrinter {
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public:
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X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI);
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StringRef getRegName(unsigned RegNo) const;
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virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
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virtual void printInst(const MCInst *MI, raw_ostream &OS);
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virtual StringRef getOpcodeName(unsigned Opcode) const;
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@ -29,8 +29,8 @@ using namespace llvm;
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#define GET_INSTRUCTION_NAME
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#include "X86GenAsmWriter1.inc"
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StringRef X86IntelInstPrinter::getRegName(unsigned RegNo) const {
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return getRegisterName(RegNo);
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void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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OS << getRegisterName(RegNo);
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}
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void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) {
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@ -27,7 +27,7 @@ public:
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X86IntelInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI)
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: MCInstPrinter(MAI) {}
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StringRef getRegName(unsigned RegNo) const;
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virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
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virtual void printInst(const MCInst *MI, raw_ostream &OS);
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virtual StringRef getOpcodeName(unsigned Opcode) const;
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