mirror of
https://github.com/RPCS3/llvm.git
synced 2025-01-26 20:57:15 +00:00
simplify call code, remove pseudo ops for div and rem, track more loads and stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22322 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
parent
5de8b9d796
commit
cf8bf388ea
@ -612,7 +612,7 @@ static void getValueInfo(const Value* v, int& type, int& fun, int& offset)
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offset = 0;
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} else if (const GlobalValue* GV = dyn_cast<GlobalValue>(v)) {
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type = 1;
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fun = 1;
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fun = 0;
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const Module* M = GV->getParent();
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int i = 0;
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for(Module::const_global_iterator ii = M->global_begin(); &*ii != GV; ++ii)
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@ -646,6 +646,8 @@ static void getValueInfo(const Value* v, int& type, int& fun, int& offset)
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++i;
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offset = i;
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}
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//type = 4: register spilling
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//type = 5: global address loading or constant loading
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}
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static int getUID()
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@ -887,8 +889,15 @@ void AlphaISel::MoveFP2Int(unsigned src, unsigned dst, bool isDouble)
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MachineFunction *F = BB->getParent();
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int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, 8);
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(0)
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.addImm(getUID());
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Opc = isDouble ? Alpha::STT : Alpha::STS;
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BuildMI(BB, Opc, 3).addReg(src).addFrameIndex(FrameIdx).addReg(Alpha::F31);
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(0)
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.addImm(getUID());
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Opc = isDouble ? Alpha::LDQ : Alpha::LDL;
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BuildMI(BB, Alpha::LDQ, 2, dst).addFrameIndex(FrameIdx).addReg(Alpha::F31);
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}
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@ -907,8 +916,15 @@ void AlphaISel::MoveInt2FP(unsigned src, unsigned dst, bool isDouble)
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MachineFunction *F = BB->getParent();
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int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, 8);
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(0)
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.addImm(getUID());
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Opc = isDouble ? Alpha::STQ : Alpha::STL;
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BuildMI(BB, Opc, 3).addReg(src).addFrameIndex(FrameIdx).addReg(Alpha::F31);
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(0)
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.addImm(getUID());
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Opc = isDouble ? Alpha::LDT : Alpha::LDS;
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BuildMI(BB, Opc, 2, dst).addFrameIndex(FrameIdx).addReg(Alpha::F31);
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}
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@ -1260,25 +1276,17 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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getValueInfo(dyn_cast<SrcValueSDNode>(N.getOperand(2))->getValue(),
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i, j, k);
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if (GlobalAddressSDNode *GASD =
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dyn_cast<GlobalAddressSDNode>(Address)) {
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if (GASD->getGlobal()->isExternal()) {
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Tmp1 = SelectExpr(Address);
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
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.addImm(getUID());
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BuildMI(BB, Opc, 2, Result).addImm(0).addReg(Tmp1);
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} else {
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Tmp1 = MakeReg(MVT::i64);
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Alpha::LDAHr, 2, Tmp1)
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.addGlobalAddress(GASD->getGlobal()).addReg(Alpha::R29);
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
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.addImm(getUID());
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BuildMI(BB, GetRelVersion(Opc), 2, Result)
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.addGlobalAddress(GASD->getGlobal()).addReg(Tmp1);
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}
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GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(Address);
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if (GASD && !GASD->getGlobal()->isExternal()) {
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Tmp1 = MakeReg(MVT::i64);
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Alpha::LDAHr, 2, Tmp1)
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.addGlobalAddress(GASD->getGlobal()).addReg(Alpha::R29);
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
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.addImm(getUID());
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BuildMI(BB, GetRelVersion(Opc), 2, Result)
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.addGlobalAddress(GASD->getGlobal()).addReg(Tmp1);
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} else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
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AlphaLowering.restoreGP(BB);
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has_sym = true;
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@ -1313,7 +1321,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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has_sym = true;
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(0).addImm(0).addImm(0)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(5).addImm(0).addImm(0)
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.addImm(getUID());
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BuildMI(BB, Alpha::LDQl, 2, Result)
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@ -1321,6 +1329,19 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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.addReg(Alpha::R29);
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return Result;
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case ISD::ExternalSymbol:
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AlphaLowering.restoreGP(BB);
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has_sym = true;
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(5).addImm(0).addImm(0)
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.addImm(getUID());
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BuildMI(BB, Alpha::LDQl, 2, Result)
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.addExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol())
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.addReg(Alpha::R29);
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return Result;
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case ISD::TAILCALL:
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case ISD::CALL:
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{
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@ -1393,27 +1414,12 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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}
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}
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//build the right kind of call
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if (GlobalAddressSDNode *GASD =
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dyn_cast<GlobalAddressSDNode>(N.getOperand(1)))
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{
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if (GASD->getGlobal()->isExternal()) {
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//use safe calling convention
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AlphaLowering.restoreGP(BB);
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has_sym = true;
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BuildMI(BB, Alpha::CALL, 1).addGlobalAddress(GASD->getGlobal());
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} else {
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//use PC relative branch call
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Alpha::BSR, 1, Alpha::R26)
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.addGlobalAddress(GASD->getGlobal(),true);
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}
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}
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else if (ExternalSymbolSDNode *ESSDN =
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dyn_cast<ExternalSymbolSDNode>(N.getOperand(1)))
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{
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GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(N.getOperand(1));
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if (GASD && !GASD->getGlobal()->isExternal()) {
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//use PC relative branch call
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AlphaLowering.restoreGP(BB);
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has_sym = true;
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BuildMI(BB, Alpha::CALL, 1).addExternalSymbol(ESSDN->getSymbol(), true);
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BuildMI(BB, Alpha::BSR, 1, Alpha::R26)
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.addGlobalAddress(GASD->getGlobal(),true);
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} else {
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//no need to restore GP as we are doing an indirect call
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Tmp1 = SelectExpr(N.getOperand(1));
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@ -1886,26 +1892,27 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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}
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//else fall though
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case ISD::UREM:
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case ISD::SREM:
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//FIXME: alpha really doesn't support any of these operations,
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// the ops are expanded into special library calls with
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// special calling conventions
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//Restore GP because it is a call after all...
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case ISD::SREM: {
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const char* opstr = 0;
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switch(opcode) {
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case ISD::UREM: Opc = Alpha::REMQU; break;
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case ISD::SREM: Opc = Alpha::REMQ; break;
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case ISD::UDIV: Opc = Alpha::DIVQU; break;
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case ISD::SDIV: Opc = Alpha::DIVQ; break;
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case ISD::UREM: opstr = "__remqu"; break;
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case ISD::SREM: opstr = "__remq"; break;
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case ISD::UDIV: opstr = "__divqu"; break;
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case ISD::SDIV: opstr = "__divq"; break;
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}
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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SDOperand Addr =
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ISelDAG->getExternalSymbol(opstr, AlphaLowering.getPointerTy());
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Tmp3 = SelectExpr(Addr);
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//set up regs explicitly (helps Reg alloc)
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BuildMI(BB, Alpha::BIS, 2, Alpha::R24).addReg(Tmp1).addReg(Tmp1);
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BuildMI(BB, Alpha::BIS, 2, Alpha::R25).addReg(Tmp2).addReg(Tmp2);
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Opc, 2).addReg(Alpha::R24).addReg(Alpha::R25);
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BuildMI(BB, Alpha::BIS, 2, Alpha::R27).addReg(Tmp3).addReg(Tmp3);
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BuildMI(BB, Alpha::JSRs, 2, Alpha::R23).addReg(Alpha::R27).addImm(0);
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BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R27).addReg(Alpha::R27);
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return Result;
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}
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case ISD::FP_TO_UINT:
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case ISD::FP_TO_SINT:
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@ -2095,6 +2102,9 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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Tmp1 = MakeReg(MVT::i64);
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BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CPI)
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.addReg(Alpha::R29);
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(5).addImm(0).addImm(0)
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.addImm(getUID());
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BuildMI(BB, Alpha::LDQr, 2, Result).addConstantPoolIndex(CPI)
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.addReg(Tmp1);
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}
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@ -2289,25 +2299,17 @@ void AlphaISel::Select(SDOperand N) {
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getValueInfo(dyn_cast<SrcValueSDNode>(N.getOperand(3))->getValue(),
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i, j, k);
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if (GlobalAddressSDNode *GASD =
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dyn_cast<GlobalAddressSDNode>(Address)) {
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if (GASD->getGlobal()->isExternal()) {
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Tmp2 = SelectExpr(Address);
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
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.addImm(getUID());
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BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(0).addReg(Tmp2);
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} else {
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Tmp2 = MakeReg(MVT::i64);
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Alpha::LDAHr, 2, Tmp2)
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.addGlobalAddress(GASD->getGlobal()).addReg(Alpha::R29);
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
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.addImm(getUID());
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BuildMI(BB, GetRelVersion(Opc), 3).addReg(Tmp1)
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.addGlobalAddress(GASD->getGlobal()).addReg(Tmp2);
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}
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GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(Address);
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if (GASD && !GASD->getGlobal()->isExternal()) {
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Tmp2 = MakeReg(MVT::i64);
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Alpha::LDAHr, 2, Tmp2)
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.addGlobalAddress(GASD->getGlobal()).addReg(Alpha::R29);
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
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.addImm(getUID());
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BuildMI(BB, GetRelVersion(Opc), 3).addReg(Tmp1)
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.addGlobalAddress(GASD->getGlobal()).addReg(Tmp2);
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} else if(Address.getOpcode() == ISD::FrameIndex) {
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
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@ -45,15 +45,6 @@ let Defs = [R29] in
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let Uses = [R27] in
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def LDGP : PseudoInstAlpha<(ops), "ldgp $$29, 0($$27)">;
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let isCall = 1,
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Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19,
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R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,
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F0, F1,
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F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
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F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30],
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Uses = [R29] in
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def CALL : PseudoInstAlpha< (ops s64imm:$TARGET), "jsr $TARGET">; //Jump to subroutine
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//RESULTS of these go to R27
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//These are also evil as the assembler expands them into calls
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let Uses = [R29],
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@ -305,6 +296,9 @@ let isCall = 1,
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def JSR : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr $RD,($RS),$DISP">; //Jump to subroutine
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def BSR : BForm<0x34, (ops GPRC:$RD, s21imm:$DISP), "bsr $RD,$DISP">; //Branch to subroutine
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}
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let isCall = 1, Defs = [R24, R25, R27, R28], Uses = [R24, R25] in
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def JSRs : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr $RD,($RS),$DISP">; //Jump to div or rem
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def JSR_COROUTINE : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS), "jsr_coroutine $RD,($RS),1">; //Jump to subroutine return
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def BR : BForm<0x30, (ops GPRC:$RD, s21imm:$DISP), "br $RD,$DISP">; //Branch
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@ -31,6 +31,10 @@
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#include <iostream>
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using namespace llvm;
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namespace llvm {
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extern cl::opt<bool> EnableAlphaLSMark;
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}
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//These describe LDAx
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static const int IMM_LOW = -32768;
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static const int IMM_HIGH = 32767;
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@ -50,6 +54,12 @@ static long getLower16(long l)
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return l - h * IMM_MULT;
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}
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static int getUID()
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{
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static int id = 0;
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return ++id;
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}
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AlphaRegisterInfo::AlphaRegisterInfo()
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: AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP)
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{
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@ -68,6 +78,9 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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unsigned SrcReg, int FrameIdx) const {
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//std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n";
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//BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
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if (EnableAlphaLSMark)
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BuildMI(MBB, MI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(1)
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.addImm(getUID());
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if (getClass(SrcReg) == Alpha::FPRCRegisterClass)
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BuildMI(MBB, MI, Alpha::STT, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
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else if (getClass(SrcReg) == Alpha::GPRCRegisterClass)
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@ -81,6 +94,9 @@ AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx) const{
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//std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n";
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if (EnableAlphaLSMark)
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BuildMI(MBB, MI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(2)
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.addImm(getUID());
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if (getClass(DestReg) == Alpha::FPRCRegisterClass)
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BuildMI(MBB, MI, Alpha::LDT, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
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else if (getClass(DestReg) == Alpha::GPRCRegisterClass)
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