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Fix ARMFastISel::ARMEmitIntExt shift emission
My patch 'r183551 - ARM FastISel integer sext/zext improvements' was incorrect when emitting ARM register-immediate ASR, LSL, LSR instructions: they are pseudo-instructions in ARMInstrInfo.td and I should have used MOVsi instead. This is not an issue when code is generated through a .s file, but is an issue when generated straight to a .o (-filetype=obj). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186489 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
JF Bastien
parent
8d7435e9b1
commit
d055c59544
@ -42,7 +42,6 @@
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/GetElementPtrTypeIterator.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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@ -2631,34 +2630,46 @@ unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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};
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// Table governing the instruction(s) to be emitted.
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static const struct {
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// First entry for each of the following is sext, second zext.
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uint16_t Opc[2];
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uint8_t Imm[2]; // All instructions have either a shift or a mask.
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uint8_t hasS[2]; // Some instructions have an S bit, always set it to 0.
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} OpcTbl[2][2][3] = {
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static const struct InstructionTable {
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uint32_t Opc : 16;
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uint32_t hasS : 1; // Some instructions have an S bit, always set it to 0.
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uint32_t Shift : 7; // For shift operand addressing mode, used by MOVsi.
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uint32_t Imm : 8; // All instructions have either a shift or a mask.
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} IT[2][2][3][2] = {
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{ // Two instructions (first is left shift, second is in this table).
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{ // ARM
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/* 1 */ { { ARM::ASRi, ARM::LSRi }, { 31, 31 }, { 1, 1 } },
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/* 8 */ { { ARM::ASRi, ARM::LSRi }, { 24, 24 }, { 1, 1 } },
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/* 16 */ { { ARM::ASRi, ARM::LSRi }, { 16, 16 }, { 1, 1 } }
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{ // ARM Opc S Shift Imm
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/* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 31 },
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/* 1 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 31 } },
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/* 8 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 24 },
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/* 8 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 24 } },
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/* 16 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 16 },
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/* 16 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 16 } }
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},
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{ // Thumb
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/* 1 */ { { ARM::tASRri, ARM::tLSRri }, { 31, 31 }, { 0, 0 } },
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/* 8 */ { { ARM::tASRri, ARM::tLSRri }, { 24, 24 }, { 0, 0 } },
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/* 16 */ { { ARM::tASRri, ARM::tLSRri }, { 16, 16 }, { 0, 0 } }
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{ // Thumb Opc S Shift Imm
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/* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 },
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/* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } },
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/* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 },
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/* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } },
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/* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 },
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/* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } }
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}
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},
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{ // Single instruction.
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{ // ARM
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/* 1 */ { { ARM::KILL, ARM::ANDri }, { 0, 1 }, { 0, 1 } },
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/* 8 */ { { ARM::SXTB, ARM::ANDri }, { 0, 255 }, { 0, 1 } },
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/* 16 */ { { ARM::SXTH, ARM::UXTH }, { 0, 0 }, { 0, 0 } }
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{ // ARM Opc S Shift Imm
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/* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
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/* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } },
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/* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 },
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/* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } },
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/* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 },
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/* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } }
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},
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{ // Thumb
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/* 1 */ { { ARM::KILL, ARM::t2ANDri }, { 0, 1 }, { 0, 1 } },
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/* 8 */ { { ARM::t2SXTB, ARM::t2ANDri }, { 0, 255 }, { 0, 1 } },
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/* 16 */ { { ARM::t2SXTH, ARM::t2UXTH }, { 0, 0 }, { 0, 0 } }
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{ // Thumb Opc S Shift Imm
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/* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
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/* 1 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 1 } },
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/* 8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift, 0 },
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/* 8 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },
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/* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift, 0 },
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/* 16 bit zext */ { ARM::t2UXTH , 0, ARM_AM::no_shift, 0 } }
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}
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}
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};
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@ -2673,20 +2684,28 @@ unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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"other sizes unimplemented");
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bool hasV6Ops = Subtarget->hasV6Ops();
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unsigned Bitness = countTrailingZeros(SrcBits) >> 1; // {1,8,16}=>{0,1,2}
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unsigned Bitness = SrcBits / 8; // {1,8,16}=>{0,1,2}
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assert((Bitness < 3) && "sanity-check table bounds");
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bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];
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const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr];
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unsigned Opc = OpcTbl[isSingleInstr][isThumb2][Bitness].Opc[isZExt];
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const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt];
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unsigned Opc = ITP->Opc;
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assert(ARM::KILL != Opc && "Invalid table entry");
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unsigned Imm = OpcTbl[isSingleInstr][isThumb2][Bitness].Imm[isZExt];
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unsigned hasS = OpcTbl[isSingleInstr][isThumb2][Bitness].hasS[isZExt];
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unsigned hasS = ITP->hasS;
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ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift;
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assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
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"only MOVsi has shift operand addressing mode");
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unsigned Imm = ITP->Imm;
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// 16-bit Thumb instructions always set CPSR (unless they're in an IT block).
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bool setsCPSR = &ARM::tGPRRegClass == RC;
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unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::LSLi;
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unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi;
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unsigned ResultReg;
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// MOVsi encodes shift and immediate in shift operand addressing mode.
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// The following condition has the same value when emitting two
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// instruction sequences: both are shifts.
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bool ImmIsSO = (Shift != ARM_AM::no_shift);
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// Either one or two instructions are emitted.
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// They're always of the form:
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@ -2699,13 +2718,16 @@ unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned NumInstrsEmitted = isSingleInstr ? 1 : 2;
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for (unsigned Instr = 0; Instr != NumInstrsEmitted; ++Instr) {
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ResultReg = createResultReg(RC);
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unsigned Opcode = ((0 == Instr) && !isSingleInstr) ? LSLOpc : Opc;
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bool isLsl = (0 == Instr) && !isSingleInstr;
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unsigned Opcode = isLsl ? LSLOpc : Opc;
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ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift;
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unsigned ImmEnc = ImmIsSO ? ARM_AM::getSORegOpc(ShiftAM, Imm) : Imm;
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bool isKill = 1 == Instr;
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MachineInstrBuilder MIB = BuildMI(
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*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opcode), ResultReg);
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if (setsCPSR)
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MIB.addReg(ARM::CPSR, RegState::Define);
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AddDefaultPred(MIB.addReg(SrcReg, isKill * RegState::Kill).addImm(Imm));
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AddDefaultPred(MIB.addReg(SrcReg, isKill * RegState::Kill).addImm(ImmEnc));
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if (hasS)
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AddDefaultCC(MIB);
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// Second instruction consumes the first's result.
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