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Fix up a few more spots of addrmode2 (or not) changes that were
missed. Update some comments accordingly. Fixes rdar://8652289 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118888 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -460,7 +460,7 @@ unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
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TII.get(ARM::t2LDRpci), DestReg)
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.addConstantPoolIndex(Idx));
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else
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// The extra reg and immediate are for addrmode2.
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// The extra immediate is for addrmode2.
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(ARM::LDRcp), DestReg)
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.addConstantPoolIndex(Idx)
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@ -505,11 +505,11 @@ unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
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if (RelocM == Reloc::PIC_)
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MIB.addImm(Id);
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} else {
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// The extra reg and immediate are for addrmode2.
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// The extra immediate is for addrmode2.
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MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
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DestReg)
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.addConstantPoolIndex(Idx)
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.addReg(0).addImm(0);
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.addImm(0);
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}
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AddOptionalDefs(MIB);
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return DestReg;
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@ -790,9 +790,15 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
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if (isFloat)
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Offset /= 4;
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(Opc), ResultReg)
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.addReg(Base).addImm(Offset));
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// LDRH needs an additional operand.
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if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(Opc), ResultReg)
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.addReg(Base).addReg(0).addImm(Offset));
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else
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(Opc), ResultReg)
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.addReg(Base).addImm(Offset));
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return true;
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}
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