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Revert 122353-122355 for the moment, they broke stuff.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122360 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen 2010-12-21 21:22:27 +00:00
parent 64b4412196
commit d0cf2585a0
3 changed files with 6 additions and 42 deletions
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32
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -2967,37 +2967,11 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
N0.getOperand(1).getOpcode() == ISD::Constant) {
uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
uint64_t c2 = N1C->getZExtValue();
if (c1 + c2 >= OpSizeInBits)
if (c1 + c2 > OpSizeInBits)
return DAG.getConstant(0, VT);
return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
DAG.getConstant(c1 + c2, N1.getValueType()));
}
// fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
// For this to be valid, the second form must not preserve any of the bits
// that are shifted out by the inner shift in the first form. This means
// the outer shift size must be >= the number of bits added by the ext.
// As a corollary, we don't care what kind of ext it is.
if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
N0.getOpcode() == ISD::ANY_EXTEND ||
N0.getOpcode() == ISD::SIGN_EXTEND) &&
N0.getOperand(0).getOpcode() == ISD::SHL &&
isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
uint64_t c1 =
cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
uint64_t c2 = N1C->getZExtValue();
EVT InnerShiftVT = N0.getOperand(0).getValueType();
uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
if (c2 >= OpSizeInBits - InnerShiftSize) {
if (c1 + c2 >= OpSizeInBits)
return DAG.getConstant(0, VT);
return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT,
DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT,
N0.getOperand(0)->getOperand(0)),
DAG.getConstant(c1 + c2, VT));
}
}
// fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or
// (srl (and x, (shl -1, c1)), (sub c1, c2))
if (N1C && N0.getOpcode() == ISD::SRL &&
@ -3191,7 +3165,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
N0.getOperand(1).getOpcode() == ISD::Constant) {
uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
uint64_t c2 = N1C->getZExtValue();
if (c1 + c2 >= OpSizeInBits)
if (c1 + c2 > OpSizeInBits)
return DAG.getConstant(0, VT);
return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
DAG.getConstant(c1 + c2, N1.getValueType()));
@ -3204,7 +3178,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
uint64_t c1 =
cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
uint64_t c2 = N1C->getZExtValue();
EVT InnerShiftVT = N0.getOperand(0).getValueType();
EVT InnerShiftVT = N0.getOperand(0)->getOperand(1).getValueType();
uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
// This is only valid if the OpSizeInBits + c1 = size of inner shift.
if (c1 + OpSizeInBits == InnerShiftSize) {

6
test/CodeGen/X86/divide-by-constant.ll
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@ -29,9 +29,9 @@ entry:
ret i8 %div
; CHECK: test3:
; CHECK: movzbl 8(%esp), %eax
; CHECK-NEXT: imull $171, %eax, %eax
; CHECK-NEXT: shrl $9, %eax
; CHECK: imull $171, %eax, %eax
; CHECK-NEXT: shrb %ah
; CHECK-NEXT: movzbl %ah, %eax
; CHECK-NEXT: ret
}

10
test/CodeGen/X86/x86-64-extend-shift.ll
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@ -1,10 +0,0 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
; Formerly there were two shifts.
define i64 @baz(i32 %A) nounwind {
; CHECK: shlq $49, %rax
%tmp1 = shl i32 %A, 17
%tmp2 = zext i32 %tmp1 to i64
%tmp3 = shl i64 %tmp2, 32
ret i64 %tmp3
}