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X86JITInfo::getLazyResolverFunction() should not read cpu id to determine whether sse is available. Just use consult subtarget.

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No functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80880 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-09-03 04:37:05 +00:00
parent 9bd2acb3b2
commit d0da6ff3ad
4 changed files with 25 additions and 33 deletions
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25
lib/Target/X86/X86JITInfo.cpp
View File

@ -15,6 +15,7 @@
#include "X86JITInfo.h"
#include "X86Relocations.h"
#include "X86Subtarget.h"
#include "X86TargetMachine.h"
#include "llvm/Function.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
@ -407,24 +408,14 @@ TargetJITInfo::LazyResolverFn
X86JITInfo::getLazyResolverFunction(JITCompilerFn F) {
JITCompilerFunction = F;
#if defined (X86_32_JIT) && !defined (_MSC_VER)
unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
union {
unsigned u[3];
char c[12];
} text;
return Subtarget->hasSSE1()
? X86CompilationCallback_SSE : X86CompilationCallback;
}
if (!X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1)) {
// FIXME: support for AMD family of processors.
if (memcmp(text.c, "GenuineIntel", 12) == 0) {
X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
if ((EDX >> 25) & 0x1)
return X86CompilationCallback_SSE;
}
}
#endif
return X86CompilationCallback;
X86JITInfo::X86JITInfo(X86TargetMachine &tm) : TM(tm) {
Subtarget = &TM.getSubtarget<X86Subtarget>();
useGOT = 0;
TLSOffset = 0;
}
void *X86JITInfo::emitGlobalValueIndirectSym(const GlobalValue* GV, void *ptr,

7
lib/Target/X86/X86JITInfo.h
View File

@ -20,16 +20,15 @@
namespace llvm {
class X86TargetMachine;
class X86Subtarget;
class X86JITInfo : public TargetJITInfo {
X86TargetMachine &TM;
const X86Subtarget *Subtarget;
uintptr_t PICBase;
char* TLSOffset;
public:
explicit X86JITInfo(X86TargetMachine &tm) : TM(tm) {
useGOT = 0;
TLSOffset = 0;
}
explicit X86JITInfo(X86TargetMachine &tm);
/// replaceMachineCodeForFunction - Make it so that calling the function
/// whose machine code is at OLD turns into a call to NEW, perhaps by

19
lib/Target/X86/X86Subtarget.cpp
View File

@ -158,8 +158,9 @@ unsigned X86Subtarget::getSpecialAddressLatency() const {
/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
/// specified arguments. If we can't run cpuid on the host, return true.
bool X86::GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
unsigned *rECX, unsigned *rEDX) {
bool
X86Subtarget::GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
#if defined(__GNUC__)
// gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
@ -230,10 +231,10 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
char c[12];
} text;
if (X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
if (GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
return;
X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
if ((EDX >> 15) & 1) HasCMov = true;
if ((EDX >> 23) & 1) X86SSELevel = MMX;
@ -257,22 +258,22 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
DetectFamilyModel(EAX, Family, Model);
IsBTMemSlow = IsAMD || (Family == 6 && Model >= 13);
X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
HasX86_64 = (EDX >> 29) & 0x1;
HasSSE4A = IsAMD && ((ECX >> 6) & 0x1);
HasFMA4 = IsAMD && ((ECX >> 16) & 0x1);
}
}
static const char *GetCurrentX86CPU() {
const char *X86Subtarget::GetCurrentX86CPU() {
unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
if (X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
if (GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
return "generic";
unsigned Family = 0;
unsigned Model = 0;
DetectFamilyModel(EAX, Family, Model);
X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
bool Em64T = (EDX >> 29) & 0x1;
bool HasSSE3 = (ECX & 0x1);
@ -281,7 +282,7 @@ static const char *GetCurrentX86CPU() {
char c[12];
} text;
X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
if (memcmp(text.c, "GenuineIntel", 12) == 0) {
switch (Family) {
case 3:

7
lib/Target/X86/X86Subtarget.h
View File

@ -214,14 +214,15 @@ public:
/// indicating the number of scheduling cycles of backscheduling that
/// should be attempted.
unsigned getSpecialAddressLatency() const;
};
namespace X86 {
private:
/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in
/// the specified arguments. If we can't run cpuid on the host, return true.
bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
unsigned *rECX, unsigned *rEDX);
}
const char *GetCurrentX86CPU();
};
} // End llvm namespace