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Make linear scan's trivial coalescer slightly more aggressive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62547 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -249,7 +249,7 @@ unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
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if ((cur.preference && cur.preference == Reg) || !cur.containsOneValue())
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return Reg;
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VNInfo *vni = cur.getValNumInfo(0);
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VNInfo *vni = cur.begin()->valno;
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if (!vni->def || vni->def == ~1U || vni->def == ~0U)
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return Reg;
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MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
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@ -686,13 +686,13 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
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unsigned StartPosition = cur->beginNumber();
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const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
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// If this live interval is defined by a move instruction and its source is
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// assigned a physical register that is compatible with the target register
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// class, then we should try to assign it the same register.
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// If start of this live interval is defined by a move instruction and its
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// source is assigned a physical register that is compatible with the target
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// register class, then we should try to assign it the same register.
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// This can happen when the move is from a larger register class to a smaller
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// one, e.g. X86::mov32to32_. These move instructions are not coalescable.
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if (!cur->preference && cur->containsOneValue()) {
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VNInfo *vni = cur->getValNumInfo(0);
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if (!cur->preference && cur->hasAtLeastOneValue()) {
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VNInfo *vni = cur->begin()->valno;
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if (vni->def && vni->def != ~1U && vni->def != ~0U) {
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MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
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unsigned SrcReg, DstReg;
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8
test/CodeGen/X86/uint_to_fp-2.ll
Normal file
8
test/CodeGen/X86/uint_to_fp-2.ll
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@ -0,0 +1,8 @@
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; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movsd | count 1
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; rdar://6504833
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define float @f(i32 %x) nounwind readnone {
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entry:
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%0 = uitofp i32 %x to float
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ret float %0
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}
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