More renamings of Target/Machine*Info to Target/Target*Info

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5204 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/CodeGen/RegClass.h

@@ -9,9 +9,9 @@
 #define REG_CLASS_H
 
 #include "llvm/CodeGen/InterferenceGraph.h"
-#include "llvm/Target/MachineRegInfo.h"
+#include "llvm/Target/TargetRegInfo.h"
 #include <stack>
-class MachineRegClassInfo;
+class TargetRegClassInfo;
 
 typedef std::vector<unsigned> ReservedColorListType;
 
@@ -24,7 +24,7 @@ typedef std::vector<unsigned> ReservedColorListType;
 //   This is the class that contains all data structures and common algos
 //   for coloring a particular register class (e.g., int class, fp class).  
 //   This class is hardware independent. This class accepts a hardware 
-//   dependent description of machine registers (MachineRegInfo class) to 
+//   dependent description of machine registers (TargetRegInfo class) to 
 //   get hardware specific info and to color an individual IG node.
 //
 //   This class contains the InterferenceGraph (IG).
@@ -35,7 +35,7 @@ typedef std::vector<unsigned> ReservedColorListType;
 //-----------------------------------------------------------------------------
 class RegClass {
   const Function *const Meth;           // Function we are working on
-  const MachineRegClassInfo *const MRC; // corresponding MRC
+  const TargetRegClassInfo *const MRC; // corresponding MRC
   const unsigned RegClassID;            // my int ID
 
   InterferenceGraph IG;                 // Interference graph - constructed by
@@ -69,7 +69,7 @@ class RegClass {
  public:
 
   RegClass(const Function *M,
-	   const MachineRegClassInfo *MRC,
+	   const TargetRegClassInfo *MRC,
 	   const ReservedColorListType *RCL = 0);
 
   inline void createInterferenceGraph() { IG.createGraph(); }

include/llvm/Target/TargetMachine.h

@@ -12,8 +12,8 @@
 
 class MachineInstrInfo;
 class MachineInstrDescriptor;
-class MachineSchedInfo;
-class MachineRegInfo;
+class TargetSchedInfo;
+class TargetRegInfo;
 class TargetFrameInfo;
 class TargetCacheInfo;
 class TargetOptInfo;
@@ -57,8 +57,8 @@ public:
   // -- Machine-level optimization information (peephole only)
   // 
   virtual const MachineInstrInfo&       getInstrInfo() const = 0;
-  virtual const MachineSchedInfo&       getSchedInfo() const = 0;
-  virtual const MachineRegInfo&	        getRegInfo()   const = 0;
+  virtual const TargetSchedInfo&        getSchedInfo() const = 0;
+  virtual const TargetRegInfo&          getRegInfo()   const = 0;
   virtual const TargetFrameInfo&        getFrameInfo() const = 0;
   virtual const TargetCacheInfo&        getCacheInfo() const = 0;
   virtual const TargetOptInfo&          getOptInfo()   const = 0;

include/llvm/Target/TargetRegInfo.h

@@ -1,12 +1,12 @@
-//===-- llvm/Target/RegInfo.h - Target Register Information ------*- C++ -*-==//
+//===-- llvm/Target/TargetRegInfo.h - Target Register Info -------*- C++ -*-==//
 //
 // This file is used to describe the register system of a target to the
 // register allocator.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TARGET_MACHINEREGINFO_H
-#define LLVM_TARGET_MACHINEREGINFO_H
+#ifndef LLVM_TARGET_TARGETREGINFO_H
+#define LLVM_TARGET_TARGETREGINFO_H
 
 #include "Support/NonCopyable.h"
 #include "Support/hash_map"
@@ -24,17 +24,11 @@ class MachineInstr;
 class PhyRegAlloc;
 class BasicBlock;
 
-//-----------------------------------------------------------------------------
-// class MachineRegClassInfo
-// 
-// Purpose:
-//   Interface to description of machine register class (e.g., int reg class
-//   float reg class etc)
-// 
-//--------------------------------------------------------------------------
-
-
-class MachineRegClassInfo {
+///----------------------------------------------------------------------------
+///   Interface to description of machine register class (e.g., int reg class
+///   float reg class etc)
+///
+class TargetRegClassInfo {
 protected:
   const unsigned RegClassID;        // integer ID of a reg class
   const unsigned NumOfAvailRegs;    // # of avail for coloring -without SP etc.
@@ -51,31 +45,26 @@ public:
                            std::vector<bool> &IsColorUsedArr) const = 0;
   virtual bool isRegVolatile(int Reg) const = 0;
 
-  MachineRegClassInfo(unsigned ID, unsigned NVR, unsigned NAR)
+  TargetRegClassInfo(unsigned ID, unsigned NVR, unsigned NAR)
     : RegClassID(ID), NumOfAvailRegs(NVR), NumOfAllRegs(NAR) {}
 };
 
 
 
 //---------------------------------------------------------------------------
-// class MachineRegInfo
-// 
-// Purpose:
-//   Interface to register info of target machine
-// 
-//--------------------------------------------------------------------------
-
-class MachineRegInfo : public NonCopyableV {
+/// TargetRegInfo - Interface to register info of target machine
+///
+class TargetRegInfo : public NonCopyableV {
 protected:
   // A vector of all machine register classes
   //
-  std::vector<const MachineRegClassInfo *> MachineRegClassArr;    
+  std::vector<const TargetRegClassInfo *> MachineRegClassArr;    
   
 public:
   const TargetMachine &target;
 
-  MachineRegInfo(const TargetMachine& tgt) : target(tgt) { }
-  ~MachineRegInfo() {
+  TargetRegInfo(const TargetMachine& tgt) : target(tgt) { }
+  ~TargetRegInfo() {
     for (unsigned i = 0, e = MachineRegClassArr.size(); i != e; ++i)
       delete MachineRegClassArr[i];
   }
@@ -96,7 +85,7 @@ public:
     return MachineRegClassArr.size(); 
   }  
 
-  const MachineRegClassInfo *getMachineRegClass(unsigned i) const { 
+  const TargetRegClassInfo *getMachineRegClass(unsigned i) const { 
     return MachineRegClassArr[i]; 
   }
 
@@ -136,7 +125,7 @@ public:
 
 
   // The following methods are used to generate "copy" machine instructions
-  // for an architecture. Currently they are used in MachineRegClass 
+  // for an architecture. Currently they are used in TargetRegClass 
   // interface. However, they can be moved to MachineInstrInfo interface if
   // necessary.
   //

include/llvm/Target/TargetSchedInfo.h

@@ -1,11 +1,11 @@
-//===- Target/MachineSchedInfo.h - Target Instruction Sched Info -*- C++ -*-==//
+//===- Target/TargetSchedInfo.h - Target Instruction Sched Info --*- C++ -*-==//
 //
 // This file describes the target machine to the instruction scheduler.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TARGET_MACHINESCHEDINFO_H
-#define LLVM_TARGET_MACHINESCHEDINFO_H
+#ifndef LLVM_TARGET_TARGETSCHEDINFO_H
+#define LLVM_TARGET_TARGETSCHEDINFO_H
 
 #include "llvm/Target/MachineInstrInfo.h"
 #include "Support/hash_map"
@@ -164,19 +164,15 @@ private:
     feasibleSlots.resize(maxNumSlots);
   }
   
-  friend class MachineSchedInfo;	// give access to these functions
+  friend class TargetSchedInfo;	// give access to these functions
 };
 
 
 //---------------------------------------------------------------------------
-// class MachineSchedInfo
-//
-// Purpose:
-//   Common interface to machine information for instruction scheduling
-//---------------------------------------------------------------------------
-
-class MachineSchedInfo {
-public:
+/// TargetSchedInfo - Common interface to machine information for 
+/// instruction scheduling
+///
+struct TargetSchedInfo {
   const TargetMachine& target;
   
   unsigned maxNumIssueTotal;
@@ -203,17 +199,17 @@ protected:
   }
 
 private:
-  MachineSchedInfo(const MachineSchedInfo &);  // DO NOT IMPLEMENT
-  void operator=(const MachineSchedInfo &);  // DO NOT IMPLEMENT
+  TargetSchedInfo(const TargetSchedInfo &);  // DO NOT IMPLEMENT
+  void operator=(const TargetSchedInfo &);  // DO NOT IMPLEMENT
 public:
-  /*ctor*/	   MachineSchedInfo	(const TargetMachine& tgt,
+  /*ctor*/	   TargetSchedInfo	(const TargetMachine& tgt,
                                          int                  _numSchedClasses,
 					 const InstrClassRUsage* _classRUsages,
 					 const InstrRUsageDelta* _usageDeltas,
 					 const InstrIssueDelta*  _issueDeltas,
 					 unsigned _numUsageDeltas,
 					 unsigned _numIssueDeltas);
-  /*dtor*/ virtual ~MachineSchedInfo	() {}
+  /*dtor*/ virtual ~TargetSchedInfo() {}
   
   inline const MachineInstrInfo& getInstrInfo() const {
     return *mii;

lib/CodeGen/InstrSched/InstrScheduling.cpp

@@ -340,8 +340,8 @@ public:
 
 class SchedulingManager: public NonCopyable {
 public: // publicly accessible data members
-  const unsigned int nslots;
-  const MachineSchedInfo& schedInfo;
+  const unsigned nslots;
+  const TargetSchedInfo& schedInfo;
   SchedPriorities& schedPrio;
   InstrSchedule isched;
   

lib/CodeGen/InstrSched/SchedGraph.cpp

@@ -10,7 +10,7 @@
 #include "llvm/CodeGen/InstrSelection.h"
 #include "llvm/CodeGen/MachineCodeForInstruction.h"
 #include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/Target/MachineRegInfo.h"
+#include "llvm/Target/TargetRegInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/MachineInstrInfo.h"
 #include "llvm/Function.h"

lib/CodeGen/InstrSched/SchedPriorities.h

@@ -15,7 +15,7 @@
 
 #include "SchedGraph.h"
 #include "llvm/CodeGen/InstrScheduling.h"
-#include "llvm/Target/MachineSchedInfo.h"
+#include "llvm/Target/TargetSchedInfo.h"
 #include "Support/hash_set"
 #include <list>
 

lib/CodeGen/InstrSelection/InstrSelection.cpp

@@ -12,7 +12,7 @@
 #include "llvm/CodeGen/InstrForest.h"
 #include "llvm/CodeGen/MachineCodeForInstruction.h"
 #include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/Target/MachineRegInfo.h"
+#include "llvm/Target/TargetRegInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Function.h"
 #include "llvm/iPHINode.h"

lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp

@@ -13,7 +13,7 @@
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/InstrForest.h"
 #include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MachineRegInfo.h"
+#include "llvm/Target/TargetRegInfo.h"
 #include "llvm/Target/MachineInstrInfo.h"
 #include "llvm/Constants.h"
 #include "llvm/Function.h"

lib/CodeGen/RegAlloc/LiveRangeInfo.h

@@ -25,7 +25,7 @@
 class LiveRange;
 class MachineInstr;
 class RegClass;
-class MachineRegInfo;
+class TargetRegInfo;
 class TargetMachine;
 class Value;
 class Function;
@@ -50,7 +50,7 @@ class LiveRangeInfo {
 
   std::vector<RegClass *> & RegClassList;// vector containing register classess
 
-  const MachineRegInfo& MRI;        // machine reg info
+  const TargetRegInfo& MRI;        // machine reg info
 
   std::vector<MachineInstr*> CallRetInstrList;  // a list of all call/ret instrs
 

lib/CodeGen/RegAlloc/PhyRegAlloc.h

@@ -7,9 +7,9 @@
    =====
 
  * RegisterClasses: Each RegClass accepts a 
-   MachineRegClass which contains machine specific info about that register
+   TargetRegClass which contains machine specific info about that register
    class. The code in the RegClass is machine independent and they use
-   access functions in the MachineRegClass object passed into it to get
+   access functions in the TargetRegClass object passed into it to get
    machine specific info.
 
  * Machine dependent work: All parts of the register coloring algorithm
@@ -24,7 +24,7 @@
 #include <map>
 
 class MachineFunction;
-class MachineRegInfo;
+class TargetRegInfo;
 class FunctionLiveVarInfo;
 class MachineInstr;
 class LoopInfo;
@@ -57,7 +57,7 @@ class PhyRegAlloc: public NonCopyable {
   FunctionLiveVarInfo *const LVI;       // LV information for this method 
                                         // (already computed for BBs) 
   LiveRangeInfo LRI;                    // LR info  (will be computed)
-  const MachineRegInfo &MRI;            // Machine Register information
+  const TargetRegInfo &MRI;             // Machine Register information
   const unsigned NumOfRegClasses;       // recorded here for efficiency
 
   

lib/CodeGen/RegAlloc/RegClass.cpp

@@ -14,7 +14,7 @@ using std::cerr;
 // createInterferenceGraph() above.
 //----------------------------------------------------------------------------
 RegClass::RegClass(const Function *M, 
-		   const MachineRegClassInfo *Mrc,
+		   const TargetRegClassInfo *Mrc,
 		   const ReservedColorListType *RCL)
                   :  Meth(M), MRC(Mrc), RegClassID( Mrc->getRegClassID() ),
                      IG(this), IGNodeStack(), ReservedColorList(RCL) {

lib/CodeGen/RegAlloc/RegClass.h

@@ -9,9 +9,9 @@
 #define REG_CLASS_H
 
 #include "llvm/CodeGen/InterferenceGraph.h"
-#include "llvm/Target/MachineRegInfo.h"
+#include "llvm/Target/TargetRegInfo.h"
 #include <stack>
-class MachineRegClassInfo;
+class TargetRegClassInfo;
 
 typedef std::vector<unsigned> ReservedColorListType;
 
@@ -24,7 +24,7 @@ typedef std::vector<unsigned> ReservedColorListType;
 //   This is the class that contains all data structures and common algos
 //   for coloring a particular register class (e.g., int class, fp class).  
 //   This class is hardware independent. This class accepts a hardware 
-//   dependent description of machine registers (MachineRegInfo class) to 
+//   dependent description of machine registers (TargetRegInfo class) to 
 //   get hardware specific info and to color an individual IG node.
 //
 //   This class contains the InterferenceGraph (IG).
@@ -35,7 +35,7 @@ typedef std::vector<unsigned> ReservedColorListType;
 //-----------------------------------------------------------------------------
 class RegClass {
   const Function *const Meth;           // Function we are working on
-  const MachineRegClassInfo *const MRC; // corresponding MRC
+  const TargetRegClassInfo *const MRC; // corresponding MRC
   const unsigned RegClassID;            // my int ID
 
   InterferenceGraph IG;                 // Interference graph - constructed by
@@ -69,7 +69,7 @@ class RegClass {
  public:
 
   RegClass(const Function *M,
-	   const MachineRegClassInfo *MRC,
+	   const TargetRegClassInfo *MRC,
 	   const ReservedColorListType *RCL = 0);
 
   inline void createInterferenceGraph() { IG.createGraph(); }

lib/Target/SparcV9/InstrSched/InstrScheduling.cpp

@@ -340,8 +340,8 @@ public:
 
 class SchedulingManager: public NonCopyable {
 public: // publicly accessible data members
-  const unsigned int nslots;
-  const MachineSchedInfo& schedInfo;
+  const unsigned nslots;
+  const TargetSchedInfo& schedInfo;
   SchedPriorities& schedPrio;
   InstrSchedule isched;
   

lib/Target/SparcV9/InstrSched/SchedGraph.cpp

@@ -10,7 +10,7 @@
 #include "llvm/CodeGen/InstrSelection.h"
 #include "llvm/CodeGen/MachineCodeForInstruction.h"
 #include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/Target/MachineRegInfo.h"
+#include "llvm/Target/TargetRegInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/MachineInstrInfo.h"
 #include "llvm/Function.h"

lib/Target/SparcV9/InstrSched/SchedPriorities.h

@@ -15,7 +15,7 @@
 
 #include "SchedGraph.h"
 #include "llvm/CodeGen/InstrScheduling.h"
-#include "llvm/Target/MachineSchedInfo.h"
+#include "llvm/Target/TargetSchedInfo.h"
 #include "Support/hash_set"
 #include <list>
 

lib/Target/SparcV9/InstrSelection/InstrSelection.cpp

@@ -12,7 +12,7 @@
 #include "llvm/CodeGen/InstrForest.h"
 #include "llvm/CodeGen/MachineCodeForInstruction.h"
 #include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/Target/MachineRegInfo.h"
+#include "llvm/Target/TargetRegInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Function.h"
 #include "llvm/iPHINode.h"

lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp

@@ -13,7 +13,7 @@
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/InstrForest.h"
 #include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MachineRegInfo.h"
+#include "llvm/Target/TargetRegInfo.h"
 #include "llvm/Target/MachineInstrInfo.h"
 #include "llvm/Constants.h"
 #include "llvm/Function.h"

lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h

@@ -25,7 +25,7 @@
 class LiveRange;
 class MachineInstr;
 class RegClass;
-class MachineRegInfo;
+class TargetRegInfo;
 class TargetMachine;
 class Value;
 class Function;
@@ -50,7 +50,7 @@ class LiveRangeInfo {
 
   std::vector<RegClass *> & RegClassList;// vector containing register classess
 
-  const MachineRegInfo& MRI;        // machine reg info
+  const TargetRegInfo& MRI;        // machine reg info
 
   std::vector<MachineInstr*> CallRetInstrList;  // a list of all call/ret instrs
 

lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h

@@ -7,9 +7,9 @@
    =====
 
  * RegisterClasses: Each RegClass accepts a 
-   MachineRegClass which contains machine specific info about that register
+   TargetRegClass which contains machine specific info about that register
    class. The code in the RegClass is machine independent and they use
-   access functions in the MachineRegClass object passed into it to get
+   access functions in the TargetRegClass object passed into it to get
    machine specific info.
 
  * Machine dependent work: All parts of the register coloring algorithm
@@ -24,7 +24,7 @@
 #include <map>
 
 class MachineFunction;
-class MachineRegInfo;
+class TargetRegInfo;
 class FunctionLiveVarInfo;
 class MachineInstr;
 class LoopInfo;
@@ -57,7 +57,7 @@ class PhyRegAlloc: public NonCopyable {
   FunctionLiveVarInfo *const LVI;       // LV information for this method 
                                         // (already computed for BBs) 
   LiveRangeInfo LRI;                    // LR info  (will be computed)
-  const MachineRegInfo &MRI;            // Machine Register information
+  const TargetRegInfo &MRI;             // Machine Register information
   const unsigned NumOfRegClasses;       // recorded here for efficiency
 
   

lib/Target/SparcV9/RegAlloc/RegClass.cpp

@@ -14,7 +14,7 @@ using std::cerr;
 // createInterferenceGraph() above.
 //----------------------------------------------------------------------------
 RegClass::RegClass(const Function *M, 
-		   const MachineRegClassInfo *Mrc,
+		   const TargetRegClassInfo *Mrc,
 		   const ReservedColorListType *RCL)
                   :  Meth(M), MRC(Mrc), RegClassID( Mrc->getRegClassID() ),
                      IG(this), IGNodeStack(), ReservedColorList(RCL) {

lib/Target/SparcV9/RegAlloc/RegClass.h

@@ -9,9 +9,9 @@
 #define REG_CLASS_H
 
 #include "llvm/CodeGen/InterferenceGraph.h"
-#include "llvm/Target/MachineRegInfo.h"
+#include "llvm/Target/TargetRegInfo.h"
 #include <stack>
-class MachineRegClassInfo;
+class TargetRegClassInfo;
 
 typedef std::vector<unsigned> ReservedColorListType;
 
@@ -24,7 +24,7 @@ typedef std::vector<unsigned> ReservedColorListType;
 //   This is the class that contains all data structures and common algos
 //   for coloring a particular register class (e.g., int class, fp class).  
 //   This class is hardware independent. This class accepts a hardware 
-//   dependent description of machine registers (MachineRegInfo class) to 
+//   dependent description of machine registers (TargetRegInfo class) to 
 //   get hardware specific info and to color an individual IG node.
 //
 //   This class contains the InterferenceGraph (IG).
@@ -35,7 +35,7 @@ typedef std::vector<unsigned> ReservedColorListType;
 //-----------------------------------------------------------------------------
 class RegClass {
   const Function *const Meth;           // Function we are working on
-  const MachineRegClassInfo *const MRC; // corresponding MRC
+  const TargetRegClassInfo *const MRC; // corresponding MRC
   const unsigned RegClassID;            // my int ID
 
   InterferenceGraph IG;                 // Interference graph - constructed by
@@ -69,7 +69,7 @@ class RegClass {
  public:
 
   RegClass(const Function *M,
-	   const MachineRegClassInfo *MRC,
+	   const TargetRegClassInfo *MRC,
 	   const ReservedColorListType *RCL = 0);
 
   inline void createInterferenceGraph() { IG.createGraph(); }

lib/Target/SparcV9/SparcV9Internals.h

@@ -9,10 +9,10 @@
 #define SPARC_INTERNALS_H
 
 #include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MachineSchedInfo.h"
+#include "llvm/Target/TargetSchedInfo.h"
 #include "llvm/Target/TargetFrameInfo.h"
 #include "llvm/Target/TargetCacheInfo.h"
-#include "llvm/Target/MachineRegInfo.h"
+#include "llvm/Target/TargetRegInfo.h"
 #include "llvm/Target/TargetOptInfo.h"
 #include "llvm/Type.h"
 #include <sys/types.h>
@@ -211,11 +211,11 @@ struct UltraSparcInstrInfo : public MachineInstrInfo {
 //----------------------------------------------------------------------------
 // class UltraSparcRegInfo
 //
-// This class implements the virtual class MachineRegInfo for Sparc.
+// This class implements the virtual class TargetRegInfo for Sparc.
 //
 //----------------------------------------------------------------------------
 
-class UltraSparcRegInfo : public MachineRegInfo {
+class UltraSparcRegInfo : public TargetRegInfo {
   // The actual register classes in the Sparc
   //
   enum RegClassIDs { 
@@ -511,7 +511,7 @@ public:
 //---------------------------------------------------------------------------
 
 
-class UltraSparcSchedInfo: public MachineSchedInfo {
+class UltraSparcSchedInfo: public TargetSchedInfo {
 public:
   UltraSparcSchedInfo(const TargetMachine &tgt);
 protected:
@@ -734,8 +734,8 @@ public:
   UltraSparc();
 
   virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
-  virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; }
-  virtual const MachineRegInfo   &getRegInfo()   const { return regInfo; }
+  virtual const TargetSchedInfo  &getSchedInfo() const { return schedInfo; }
+  virtual const TargetRegInfo    &getRegInfo()   const { return regInfo; }
   virtual const TargetFrameInfo  &getFrameInfo() const { return frameInfo; }
   virtual const TargetCacheInfo  &getCacheInfo() const { return cacheInfo; }
   virtual const TargetOptInfo    &getOptInfo()   const { return optInfo; }

lib/Target/SparcV9/SparcV9RegClassInfo.h

@@ -7,7 +7,7 @@
 #ifndef SPARC_REG_CLASS_INFO_H
 #define SPARC_REG_CLASS_INFO_H
 
-#include "llvm/Target/MachineRegInfo.h"
+#include "llvm/Target/TargetRegInfo.h"
 #include "llvm/CodeGen/IGNode.h"
 
 //-----------------------------------------------------------------------------
@@ -15,9 +15,9 @@
 //-----------------------------------------------------------------------------
 
 
-struct SparcIntRegClass : public MachineRegClassInfo {
+struct SparcIntRegClass : public TargetRegClassInfo {
   SparcIntRegClass(unsigned ID) 
-    : MachineRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {  }
+    : TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {  }
 
   void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const;
 
@@ -73,12 +73,12 @@ struct SparcIntRegClass : public MachineRegClassInfo {
 // Float Register Class
 //-----------------------------------------------------------------------------
 
-class SparcFloatRegClass : public MachineRegClassInfo {
+class SparcFloatRegClass : public TargetRegClassInfo {
   int findFloatColor(const LiveRange *LR, unsigned Start,
 		     unsigned End, std::vector<bool> &IsColorUsedArr) const;
 public:
   SparcFloatRegClass(unsigned ID) 
-    : MachineRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {}
+    : TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {}
 
   void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const;
 
@@ -119,9 +119,9 @@ public:
 // allocated for two names.
 //-----------------------------------------------------------------------------
 
-struct SparcIntCCRegClass : public MachineRegClassInfo {
+struct SparcIntCCRegClass : public TargetRegClassInfo {
   SparcIntCCRegClass(unsigned ID) 
-    : MachineRegClassInfo(ID, 1, 2) {  }
+    : TargetRegClassInfo(ID, 1, 2) {  }
   
   void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const {
     if (IsColorUsedArr[0])
@@ -149,9 +149,9 @@ struct SparcIntCCRegClass : public MachineRegClassInfo {
 // Only 4 Float CC registers are available
 //-----------------------------------------------------------------------------
 
-struct SparcFloatCCRegClass : public MachineRegClassInfo {
+struct SparcFloatCCRegClass : public TargetRegClassInfo {
   SparcFloatCCRegClass(unsigned ID) 
-    : MachineRegClassInfo(ID, 4, 4) {  }
+    : TargetRegClassInfo(ID, 4, 4) {  }
 
   void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const {
     for(unsigned c = 0; c != 4; ++c)

lib/Target/SparcV9/SparcV9RegInfo.cpp

@@ -25,7 +25,7 @@ using std::cerr;
 using std::vector;
 
 UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
-  : MachineRegInfo(tgt), NumOfIntArgRegs(6), 
+  : TargetRegInfo(tgt), NumOfIntArgRegs(6), 
     NumOfFloatArgRegs(32), InvalidRegNum(1000) {
    
   MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID));

lib/Target/SparcV9/SparcV9SchedInfo.cpp

@@ -700,12 +700,12 @@ static const InstrRUsageDelta SparcInstrUsageDeltas[] = {
 // Purpose:
 //   Scheduling information for the UltraSPARC.
 //   Primarily just initializes machine-dependent parameters in
-//   class MachineSchedInfo.
+//   class TargetSchedInfo.
 //---------------------------------------------------------------------------
 
 /*ctor*/
 UltraSparcSchedInfo::UltraSparcSchedInfo(const TargetMachine& tgt)
-  : MachineSchedInfo(tgt,
+  : TargetSchedInfo(tgt,
                      (unsigned int) SPARC_NUM_SCHED_CLASSES,
 		     SparcRUsageDesc,
 		     SparcInstrUsageDeltas,
@@ -733,8 +733,8 @@ UltraSparcSchedInfo::UltraSparcSchedInfo(const TargetMachine& tgt)
 void
 UltraSparcSchedInfo::initializeResources()
 {
-  // Compute MachineSchedInfo::instrRUsages and MachineSchedInfo::issueGaps
-  MachineSchedInfo::initializeResources();
+  // Compute TargetSchedInfo::instrRUsages and TargetSchedInfo::issueGaps
+  TargetSchedInfo::initializeResources();
   
   // Machine-dependent fixups go here.  None for now.
 }

lib/Target/TargetSchedInfo.cpp

@@ -5,7 +5,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "llvm/Target/MachineSchedInfo.h"
+#include "llvm/Target/TargetSchedInfo.h"
 #include "llvm/Target/TargetMachine.h"
 
 resourceId_t MachineResource::nextId = 0;
@@ -69,17 +69,17 @@ ComputeMinGap(const InstrRUsage &fromRU,
 
 
 //---------------------------------------------------------------------------
-// class MachineSchedInfo
+// class TargetSchedInfo
 //	Interface to machine description for instruction scheduling
 //---------------------------------------------------------------------------
 
-MachineSchedInfo::MachineSchedInfo(const TargetMachine&    tgt,
-                                   int                     NumSchedClasses,
-                                   const InstrClassRUsage* ClassRUsages,
-                                   const InstrRUsageDelta* UsageDeltas,
-                                   const InstrIssueDelta*  IssueDeltas,
-                                   unsigned int		   NumUsageDeltas,
-                                   unsigned int		   NumIssueDeltas)
+TargetSchedInfo::TargetSchedInfo(const TargetMachine&    tgt,
+                                 int                     NumSchedClasses,
+                                 const InstrClassRUsage* ClassRUsages,
+                                 const InstrRUsageDelta* UsageDeltas,
+                                 const InstrIssueDelta*  IssueDeltas,
+                                 unsigned NumUsageDeltas,
+                                 unsigned NumIssueDeltas)
   : target(tgt),
     numSchedClasses(NumSchedClasses), mii(& tgt.getInstrInfo()),
     classRUsages(ClassRUsages), usageDeltas(UsageDeltas),
@@ -88,7 +88,7 @@ MachineSchedInfo::MachineSchedInfo(const TargetMachine&    tgt,
 {}
 
 void
-MachineSchedInfo::initializeResources()
+TargetSchedInfo::initializeResources()
 {
   assert(MAX_NUM_SLOTS >= (int)getMaxNumIssueTotal()
 	 && "Insufficient slots for static data! Increase MAX_NUM_SLOTS");
@@ -111,7 +111,7 @@ MachineSchedInfo::initializeResources()
 
 
 void
-MachineSchedInfo::computeInstrResources(const std::vector<InstrRUsage>&
+TargetSchedInfo::computeInstrResources(const std::vector<InstrRUsage>&
 					instrRUForClasses)
 {
   int numOpCodes =  mii->getNumRealOpCodes();
@@ -141,7 +141,7 @@ MachineSchedInfo::computeInstrResources(const std::vector<InstrRUsage>&
 
 
 void
-MachineSchedInfo::computeIssueGaps(const std::vector<InstrRUsage>&
+TargetSchedInfo::computeIssueGaps(const std::vector<InstrRUsage>&
 				   instrRUForClasses)
 {
   int numOpCodes =  mii->getNumRealOpCodes();

lib/Target/X86/X86TargetMachine.h

@@ -23,8 +23,8 @@ public:
     return &InstrInfo.getRegisterInfo();
   }
 
-  virtual const MachineSchedInfo &getSchedInfo() const { abort(); }
-  virtual const MachineRegInfo   &getRegInfo()   const { abort(); }
+  virtual const TargetSchedInfo &getSchedInfo()  const { abort(); }
+  virtual const TargetRegInfo   &getRegInfo()    const { abort(); }
   virtual const TargetCacheInfo  &getCacheInfo() const { abort(); }
   virtual const TargetOptInfo    &getOptInfo()   const { abort(); }