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[mips] [IAS] Add support for LASym with identical source and destination register operands.

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Summary:
In this case, we're supposed to load the address of the symbol in AT and then ADDu it with the source register and
put it in the destination register.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9366

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240273 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Toma Tabacu 2015-06-22 12:08:39 +00:00
parent 4f1ddd396b
commit d174678830
2 changed files with 26 additions and 8 deletions
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28
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@ -1991,6 +1991,18 @@ bool MipsAsmParser::loadAndAddSymbolAddress(
const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::create(
&Symbol->getSymbol(), MCSymbolRefExpr::VK_Mips_ABS_LO, getContext());
bool UseSrcReg = SrcReg != Mips::NoRegister;
unsigned TmpReg = DstReg;
if (UseSrcReg && (DstReg == SrcReg)) {
// At this point we need AT to perform the expansions and we exit if it is
// not available.
unsigned ATReg = getATReg(IDLoc);
if (!ATReg)
return true;
TmpReg = ATReg;
}
if (!Is32BitSym) {
// If it's a 64-bit architecture, expand to:
// la d,sym => lui d,highest(sym)
@ -2005,31 +2017,31 @@ bool MipsAsmParser::loadAndAddSymbolAddress(
&Symbol->getSymbol(), MCSymbolRefExpr::VK_Mips_HIGHER, getContext());
tmpInst.setOpcode(Mips::LUi);
tmpInst.addOperand(MCOperand::createReg(DstReg));
tmpInst.addOperand(MCOperand::createReg(TmpReg));
tmpInst.addOperand(MCOperand::createExpr(HighestExpr));
Instructions.push_back(tmpInst);
createLShiftOri<0>(MCOperand::createExpr(HigherExpr), DstReg, SMLoc(),
createLShiftOri<0>(MCOperand::createExpr(HigherExpr), TmpReg, SMLoc(),
Instructions);
createLShiftOri<16>(MCOperand::createExpr(HiExpr), DstReg, SMLoc(),
createLShiftOri<16>(MCOperand::createExpr(HiExpr), TmpReg, SMLoc(),
Instructions);
createLShiftOri<16>(MCOperand::createExpr(LoExpr), DstReg, SMLoc(),
createLShiftOri<16>(MCOperand::createExpr(LoExpr), TmpReg, SMLoc(),
Instructions);
} else {
// Otherwise, expand to:
// la d,sym => lui d,hi16(sym)
// ori d,d,lo16(sym)
tmpInst.setOpcode(Mips::LUi);
tmpInst.addOperand(MCOperand::createReg(DstReg));
tmpInst.addOperand(MCOperand::createReg(TmpReg));
tmpInst.addOperand(MCOperand::createExpr(HiExpr));
Instructions.push_back(tmpInst);
createLShiftOri<0>(MCOperand::createExpr(LoExpr), DstReg, SMLoc(),
createLShiftOri<0>(MCOperand::createExpr(LoExpr), TmpReg, SMLoc(),
Instructions);
}
if (SrcReg != Mips::NoRegister)
createAddu(DstReg, DstReg, SrcReg, Instructions);
if (UseSrcReg)
createAddu(DstReg, TmpReg, SrcReg, Instructions);
return false;
}

6
test/MC/Mips/mips-expansions.s
View File

@ -49,6 +49,12 @@
# CHECK: ori $8, $8, %lo(symbol) # encoding: [A,A,0x08,0x35]
# CHECK: # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16
# CHECK: addu $8, $8, $9 # encoding: [0x21,0x40,0x09,0x01]
la $8, symbol($8)
# CHECK: lui $1, %hi(symbol) # encoding: [A,A,0x01,0x3c]
# CHECK: # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16
# CHECK: ori $1, $1, %lo(symbol) # encoding: [A,A,0x21,0x34]
# CHECK: # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16
# CHECK: addu $8, $1, $8 # encoding: [0x21,0x40,0x28,0x00]
# LW/SW and LDC1/SDC1 of symbol address, done by MipsAsmParser::expandMemInst():
.set noat