Print a nl before pic labels so they start at a new line. This makes assembly more readable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80350 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-08-28 06:59:37 +00:00
parent 79331b2fcd
commit d17479e845
3 changed files with 12 additions and 12 deletions

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@ -529,42 +529,42 @@ PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), NoItinerary,
// Address computation and loads and stores in PIC mode.
let isNotDuplicable = 1 in {
def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
Pseudo, IIC_iALUr, "$cp:\n\tadd$p $dst, pc, $a",
Pseudo, IIC_iALUr, "\n$cp:\n\tadd$p $dst, pc, $a",
[(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
let AddedComplexity = 10 in {
let canFoldAsLoad = 1 in
def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, IIC_iLoadr, "${addr:label}:\n\tldr$p $dst, $addr",
Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr$p $dst, $addr",
[(set GPR:$dst, (load addrmodepc:$addr))]>;
def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, IIC_iLoadr, "${addr:label}:\n\tldr${p}h $dst, $addr",
Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}h $dst, $addr",
[(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, IIC_iLoadr, "${addr:label}:\n\tldr${p}b $dst, $addr",
Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}b $dst, $addr",
[(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, IIC_iLoadr, "${addr:label}:\n\tldr${p}sh $dst, $addr",
Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}sh $dst, $addr",
[(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, IIC_iLoadr, "${addr:label}:\n\tldr${p}sb $dst, $addr",
Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}sb $dst, $addr",
[(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
}
let AddedComplexity = 10 in {
def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Pseudo, IIC_iStorer, "${addr:label}:\n\tstr$p $src, $addr",
Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr$p $src, $addr",
[(store GPR:$src, addrmodepc:$addr)]>;
def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Pseudo, IIC_iStorer, "${addr:label}:\n\tstr${p}h $src, $addr",
Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr${p}h $src, $addr",
[(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Pseudo, IIC_iStorer, "${addr:label}:\n\tstr${p}b $src, $addr",
Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr${p}b $src, $addr",
[(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
}
} // isNotDuplicable = 1

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@ -130,7 +130,7 @@ PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
// For both thumb1 and thumb2.
let isNotDuplicable = 1 in
def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr,
"$cp:\n\tadd $dst, pc",
"\n$cp:\n\tadd $dst, pc",
[(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
// PC relative add.

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@ -384,13 +384,13 @@ multiclass T2I_st<string opc, PatFrag opnode> {
/// T2I_picld - Defines the PIC load pattern.
class T2I_picld<string opc, PatFrag opnode> :
T2I<(outs GPR:$dst), (ins addrmodepc:$addr), IIC_iLoadi,
!strconcat("${addr:label}:\n\t", opc), " $dst, $addr",
!strconcat("\n${addr:label}:\n\t", opc), " $dst, $addr",
[(set GPR:$dst, (opnode addrmodepc:$addr))]>;
/// T2I_picst - Defines the PIC store pattern.
class T2I_picst<string opc, PatFrag opnode> :
T2I<(outs), (ins GPR:$src, addrmodepc:$addr), IIC_iStorer,
!strconcat("${addr:label}:\n\t", opc), " $src, $addr",
!strconcat("\n${addr:label}:\n\t", opc), " $src, $addr",
[(opnode GPR:$src, addrmodepc:$addr)]>;