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Use conservative size estimate for tBR_JTr.

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This pseudo-instruction contains a .align directive in its expansion, so
the total size may vary by 2 bytes.

It is too difficult to accurately keep track of this alignment
directive, just use the worst-case size instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145971 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2011-12-06 21:55:39 +00:00
parent 305e5fe797
commit d25c27807e
2 changed files with 4 additions and 26 deletions
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6
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -601,12 +601,12 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
assert(JTI < JT.size());
// Thumb instructions are 2 byte aligned, but JT entries are 4 byte
// 4 aligned. The assembler / linker may add 2 byte padding just before
// the JT entries. The size does not include this padding; the
// constant islands pass does separate bookkeeping for it.
// the JT entries. The size includes the worst case size of this padding.
// FIXME: If we know the size of the function is less than (1 << 16) *2
// bytes, we can use 16-bit entries instead. Then there won't be an
// alignment issue.
unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
// tBR_JT is 2 bytes + 2 bytes worst case padding for table alignment.
unsigned InstSize = (Opc == ARM::t2BR_JT) ? 2 : 4;
unsigned NumEntries = getNumJTEntries(JT, JTI);
if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
// Make sure the instruction that follows TBB is 2-byte aligned.

24
lib/Target/ARM/ARMConstantIslandPass.cpp
View File

@ -525,13 +525,8 @@ void ARMConstantIslands::InitialFunctionScan(MachineFunction &MF,
// A Thumb1 table jump may involve padding; for the offsets to
// be right, functions containing these must be 4-byte aligned.
// tBR_JTr expands to a mov pc followed by .align 2 and then the jump
// table entries. So this code checks whether offset of tBR_JTr + 2
// is aligned. That is held in Offset+MBBSize, which already has
// 2 added in for the size of the mov pc instruction.
// table entries. GetInstSizeInBytes returns the worst case size.
MF.EnsureAlignment(2U);
if ((Offset+MBBSize)%4 != 0 || HasInlineAsm)
// FIXME: Add a pseudo ALIGN instruction instead.
MBBSize += 2; // padding
continue; // Does not get an entry in ImmBranches
case ARM::t2BR_JT:
T2JumpTables.push_back(I);
@ -809,23 +804,6 @@ MachineBasicBlock *ARMConstantIslands::SplitBlockBeforeInstr(MachineInstr *MI) {
// Set the size of NewBB in BBSizes. It does not include any padding now.
BBSizes[NewBBI] = NewBBSize;
MachineInstr* ThumbJTMI = prior(NewBB->end());
if (ThumbJTMI->getOpcode() == ARM::tBR_JTr) {
// We've added another 2-byte instruction before this tablejump, which
// means we will always need padding if we didn't before, and vice versa.
// The original offset of the jump instruction was:
unsigned OrigOffset = BBOffsets[OrigBBI] + BBSizes[OrigBBI] - delta;
if (OrigOffset%4 == 0) {
// We had padding before and now we don't. No net change in code size.
delta = 0;
} else {
// We didn't have padding before and now we do.
BBSizes[NewBBI] += 2;
delta = 4;
}
}
// All BBOffsets following these blocks must be modified.
if (delta)
AdjustBBOffsetsAfter(NewBB, delta);